公开(公告)号：US20240372565A1

公开(公告)日：2024-11-07

申请号：US18141757

申请日：2023-05-01

Applicant: Mellanox Technologies, Ltd.

Inventor： Oz Harel ,  Hananel Faig ,  Yair Yakoby

IPC: H03M13/15 ,  H03M13/11

Abstract: A receiver including an equalization component to receive a signal comprising a sequence of samples corresponding to symbols and generate an equalized signal with an estimated sequence of symbols corresponding to the signal. The receiver further includes a decision generation component to detect that an aggregate error level associated with the equalized signal exceeds a saturation threshold level. The decision generation component identifies a set of errors including a first error associated with a first symbol having a highest error level and a last error associated with a last symbol. The decision generation component generates, based on the equalized signal, a decision including a sequence of one or more bits that represent each symbol of a first subset of the sequence of symbols and a confidence level corresponding to the decision, where the confidence level is based at least in part on a distance between an error level of each symbol and a level of the first error.

公开(公告)号：US12034575B2

公开(公告)日：2024-07-09

申请号：US18079304

申请日：2022-12-12

Applicant: Mellanox Technologies, Ltd.

Inventor： Hananel Faig ,  Yair Yakoby ,  Oz Harel

IPC: H04L25/03

CPC classification number: H04L25/03885 ,  H04L25/03273 ,  H04L25/03853

Abstract: A receiver includes an analog-to-digital converter (ADC) to generate a digital output, including a set of bits corresponding to a received signal. The receiver further includes a calculator circuit coupled to the ADC, the calculator circuit to calculate a set of tap coefficient gradient values corresponding to the digital output, generate a first feedback signal corresponding to the set of tap coefficient gradient values, and generate a second feedback signal corresponding to the set of tap coefficient gradient values. The receiver further includes a clock data recovery (CDR) circuit, coupled to the calculator circuit, the CDR circuit to detect a first parameter of the received signal based on the first feedback signal. The receiver further includes a feed forward equalization (FFE) system, coupled to the calculator circuit, the FFE system including multiple filter taps having a set of filter tap coefficients to be adapted based on the second feedback signal to generate a set of adapted filter tap coefficients.

公开(公告)号：US20240195663A1

公开(公告)日：2024-06-13

申请号：US18079304

申请日：2022-12-12

Applicant: Mellanox Technologies, Ltd.

Inventor： Hananel Faig ,  Yair Yakoby ,  Oz Harel

IPC: H04L25/03

CPC classification number: H04L25/03885 ,  H04L25/03273 ,  H04L25/03853

Abstract: A receiver includes an analog-to-digital converter (ADC) to generate a digital output, including a set of bits corresponding to a received signal. The receiver further includes a calculator circuit coupled to the ADC, the calculator circuit to calculate a set of tap coefficient gradient values corresponding to the digital output, generate a first feedback signal corresponding to the set of tap coefficient gradient values, and generate a second feedback signal corresponding to the set of tap coefficient gradient values. The receiver further includes a clock data recovery (CDR) circuit, coupled to the calculator circuit, the CDR circuit to detect a first parameter of the received signal based on the first feedback signal. The receiver further includes a feed forward equalization (FFE) system, coupled to the calculator circuit, the FFE system including multiple filter taps having a set of filter tap coefficients to be adapted based on the second feedback signal to generate a set of adapted filter tap coefficients

公开(公告)号：US12003355B2

公开(公告)日：2024-06-04

申请号：US17850406

申请日：2022-06-27

Applicant: Mellanox Technologies, Ltd.

Inventor： Oz Harel ,  Hananel Faig ,  Yair Yakoby

IPC: H04L25/03 ,  H04L1/00 ,  H04L1/20 ,  H04L27/01

CPC classification number: H04L25/03987 ,  H04L1/0054 ,  H04L1/203 ,  H04L27/01

Abstract: A receiver including an equalization component to receive a signal comprising a sequence of samples corresponding to symbols and generate an equalized signal with an estimated sequence of symbols corresponding to the signal. The receiver further includes a decision generation component to receive the equalized signal and generate, based on the equalized signal, a decision comprising a sequence of one or more bits that represent each symbol of the sequence of symbols and a confidence level corresponding to the decision.

公开(公告)号：US11742869B2

公开(公告)日：2023-08-29

申请号：US17573212

申请日：2022-01-11

Applicant: Mellanox Technologies, Ltd.

Inventor： Anthony Eugene Zortea ,  Hananel Faig ,  Boris Sharav ,  Mor Goren ,  Alik Gorshtein ,  Nir Sheffi

IPC: H03M1/06 ,  H03M1/10

CPC classification number: H03M1/0624 ,  H03M1/1023

Abstract: A transmitter including a digital-to-analog converter (DAC) to generate an analog output corresponding to a transmitted signal. The transmitter further includes an analog-to-digital converter (ADC) coupled to the DAC. The ADC measures the analog output of the DAC to identify a set of digital samples. The ADC identifies, from the set of digital samples, a set of valid samples, wherein each valid sample has a voltage within a voltage range. The ADC extracts one or more signal properties from the set of valid samples.

公开(公告)号：US20220286268A1

公开(公告)日：2022-09-08

申请号：US17189313

申请日：2021-03-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Hananel Faig ,  Raanan Ivry

IPC: H04L7/00 ,  H04B17/29

Abstract: A signal processing method includes receiving a digital signal including a sequence of samples. For each sample among at least some of the samples, a neighbor-based estimate is calculated over (i) one or more samples that precede the sample in the sequence and (ii) one or more samples that succeed the sample in the sequence, and an error value, indicative of a deviation of the neighbor-based estimate from an actual value of the sample, is calculating. An impairment in the digital signal is estimated based on a plurality of error values calculated for a plurality of the samples.

公开(公告)号：US11070224B1

公开(公告)日：2021-07-20

申请号：US16868894

申请日：2020-05-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Hananel Faig ,  Adam Kaminer ,  David (Dima) Rochlin ,  Raanan Ivry

IPC: H03M1/00 ,  H03M1/12 ,  H03M1/20 ,  H03M1/06

Abstract: A method for providing back-compatibility for rational sampling rate disparities between two circuitries, comprises: a) providing a Phase Locked Loop (PLL) operating at a rate different than that of the Symbols generator, which is coupled to a Digital to Analog Converter (DAC) or an Analog to Digital Converter (ADC); b) providing an interpolation filter coupled to said converter, which filter is adapted to perform sampling rate conversion operations on the samples using zero-stuffing, filtering, and decimation, or the like computation-saving algorithm; and c) obtaining the sampling of the symbols at the required and compatible rate.