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公开(公告)号：US09904646B2
公开(公告)日：2018-02-27
申请号：US13627378
申请日：2012-09-26
Applicant: Microchip Technology Incorporated
Inventor： Michael Simmons
CPC classification number: G06F13/4068
Abstract: A microcontroller includes a general purpose input/output (GPIO) port having a plurality of bits coupled to a plurality of external pins; a first set of registers for providing at least one of first control and data input/output functionality of the GPIO port; a second set of registers for providing at least one of second control and data input/output functionality of the GPIO port; and a multiplexer and associated select register for controlling the multiplexer to control said GPIO port through either said first or second register set.
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12.发明授权公开(公告)号：US09602895B2
公开(公告)日：2017-03-21
申请号：US14538253
申请日：2014-11-11
Applicant: Microchip Technology Incorporated
Inventor： Stephen Bowling , Michael Simmons
CPC classification number: H04Q9/00 , G01R22/066 , G08B13/00
Abstract: If an enclosure of a metering device is opened or vandalized, application software must determine when the metering history information became unreliable, and further notification to the utility may be desirable. Likewise, a shipping container or suitcase that has been opened or mishandled during shipping transient may be attributed to a particular location and/or handling person(s) when the time and date of the mishandling occurrence are known. A transition on a special device input from a tamper or mishandling sensor captures real-time clock/calendar (RTCC) information that provides to a software application the time and date of the detected tampering or mishandling event. This transition may also cause memory storage of the RTCC information related to the event. Thus, an integrated circuit device, for example a microcontroller or any other integrated circuit device may comprise such an RTCC and external input, and, optionally, memory storage of the RTCC event occurrence.
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公开(公告)号：US10339087B2
公开(公告)日：2019-07-02
申请号：US15901222
申请日：2018-02-21
Applicant: Microchip Technology Incorporated
Inventor： Michael Simmons
IPC: G06F13/40
Abstract: A microcontroller includes a general purpose input/output (GPIO) port having a plurality of bits coupled to a plurality of external pins; a first set of registers for providing at least one of first control and data input/output functionality of the GPIO port; a second set of registers for providing at least one of second control and data input/output functionality of the GPIO port; and a multiplexer and associated select register for controlling the multiplexer to control said GPIO port through either said first or second register set.
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公开(公告)号：US10042784B2
公开(公告)日：2018-08-07
申请号：US14880699
申请日：2015-10-12
Applicant: Microchip Technology Incorporated
Inventor： Michael Simmons , Swaroop Adusumilli
IPC: G06F13/12 , G06F13/42 , G06F13/38 , G06F5/06 , G06F13/362
CPC classification number: G06F13/12 , G06F5/065 , G06F13/362 , G06F13/385 , G06F13/4282 , G06F2205/067
Abstract: A system may provide side channel access of a Universal Serial Bus (USB) device using USB streams. The system may include a USB interface with a USB device controller, an internal bus, a logical unit number (LUN) arbiter coupled between the USB controller and the internal bus, and a secondary interface coupled with the LUN arbiter. The system may include a plurality of storage devices coupled to the internal bus. The system may provide access to the storage devices via both the USB device controller and the secondary interface. The LUN arbiter may accept a plurality of USB streams (e.g., storage device access requests) from the USB device controller and at least one additional USB stream (e.g., storage device access request) from the secondary interface. The LUN arbiter may determine a priority of access between USB streams originating from the USB device controller and the secondary interface.
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公开(公告)号：US20160103772A1
公开(公告)日：2016-04-14
申请号：US14880699
申请日：2015-10-12
Applicant: Microchip Technology Incorporated
Inventor： Michael Simmons , Swaroop Adusumilli
CPC classification number: G06F13/12 , G06F5/065 , G06F13/362 , G06F13/385 , G06F13/4282 , G06F2205/067
Abstract: A system may provide side channel access of a Universal Serial Bus (USB) device using USB streams. The system may include a USB interface with a USB device controller, an internal bus, a logical unit number (LUN) arbiter coupled between the USB controller and the internal bus, and a secondary interface coupled with the LUN arbiter. The system may include a plurality of storage devices coupled to the internal bus. The system may provide access to the storage devices via both the USB device controller and the secondary interface. The LUN arbiter may accept a plurality of USB streams (e.g., storage device access requests) from the USB device controller and at least one additional USB stream (e.g., storage device access request) from the secondary interface. The LUN arbiter may determine a priority of access between USB streams originating from the USB device controller and the secondary interface.
Abstract translation: 系统可以使用USB流提供通用串行总线（USB）设备的侧通道访问。 该系统可以包括具有USB设备控制器的USB接口，内部总线，耦合在USB控制器和内部总线之间的逻辑单元号（LUN）仲裁器，以及与LUN仲裁器耦合的辅助接口。 该系统可以包括耦合到内部总线的多个存储设备。 系统可以通过USB设备控制器和辅助接口来提供对存储设备的访问。 LUN仲裁器可以接收来自USB设备控制器的多个USB流（例如，存储设备访问请求）和来自次要接口的至少一个附加USB流（例如，存储设备访问请求）。 LUN仲裁器可以确定源自USB设备控制器的USB流与辅助接口之间的访问优先级。
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Patent Agency Ranking
公开(公告)号：US09286241B2
公开(公告)日：2016-03-15
申请号：US13771572
申请日：2013-02-20
Applicant: Microchip Technology Incorporated
Inventor： Michael Simmons
CPC classification number: G06F12/1408 , G06F21/00 , G06F21/602 , G06F21/606 , G06F21/72 , G06F2221/2113 , H04L9/0822
Abstract: A microcontroller includes on-chip key storage slots stored in a non-volatile memory, wherein selecting which key is to be used is restricted to software, wherein a predetermined key storage slot stores a Key Encrypt Key (KEK), and a register flag is provided for determining whether the predetermined key storage slot stores a key for encrypting/decrypting data or the KEK for encrypting/decrypting a key.
Abstract translation: 微控制器包括存储在非易失性存储器中的片上密钥存储时隙，其中选择要使用的密钥是限于软件，其中预定的密钥存储时隙存储密钥加密密钥（KEK），寄存器标志是 用于确定预定密钥存储时隙是否存储用于加密/解密数据的密钥或用于加密/解密密钥的KEK。
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公开(公告)号：US20130219189A1
公开(公告)日：2013-08-22
申请号：US13771572
申请日：2013-02-20
Applicant: Microchip Technology Incorporated
Inventor： Michael Simmons
IPC: G06F12/14
CPC classification number: G06F12/1408 , G06F21/00 , G06F21/602 , G06F21/606 , G06F21/72 , G06F2221/2113 , H04L9/0822
Abstract: A microcontroller includes on-chip key storage slots stored in a non-volatile memory, wherein selecting which key is to be used is restricted to software, wherein a predetermined key storage slot stores a Key Encrypt Key (KEK), and a register flag is provided for determining whether the predetermined key storage slot stores a key for encrypting/decrypting data or the KEK for encrypting/decrypting a key
Abstract translation: 微控制器包括存储在非易失性存储器中的片上密钥存储时隙，其中选择要使用的密钥是限于软件，其中预定的密钥存储时隙存储密钥加密密钥（KEK），寄存器标志是 用于确定预定密钥存储时隙是否存储用于加密/解密数据的密钥或用于加密/解密密钥的KEK
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公开(公告)号：US20130080677A1
公开(公告)日：2013-03-28
申请号：US13627378
申请日：2012-09-26
Applicant: Microchip Technology Incorporated
Inventor： Michael Simmons
IPC: G06F13/20
CPC classification number: G06F13/4068
Abstract: A microcontroller includes a general purpose input/output (GPIO) port having a plurality of bits coupled to a plurality of external pins; a first set of registers for providing at least one of first control and data input/output functionality of the GPIO port; a second set of registers for providing at least one of second control and data input/output functionality of the GPIO port; and a multiplexer and associated select register for controlling the multiplexer to control said GPIO port through either said first or second register set.
Abstract translation: 微控制器包括具有耦合到多个外部引脚的多个位的通用输入/输出（GPIO）端口; 用于提供GPIO端口的第一控制和数据输入/输出功能中的至少一个的第一组寄存器; 第二组寄存器，用于提供GPIO端口的第二控制和数据输入/输出功能中的至少一个; 以及多路复用器和相关联的选择寄存器，用于控制多路复用器以通过所述第一或第二寄存器组来控制所述GPIO端口。
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公开(公告)号：US20230251977A1
公开(公告)日：2023-08-10
申请号：US18136446
申请日：2023-04-19
Applicant: Microchip Technology Incorporated
Inventor： Michael Simmons
CPC classification number: G06F12/1416 , G06F3/0679 , G06F3/0653 , G06F3/0659 , G06F3/0616
Abstract: An apparatus includes a database with device profiles, and a device programmer. The device programmer includes instructions. The instructions, when read and executed by a processor, cause the device programmer to identify a device identifier of an electronic device. The device programmer is further caused to, based upon the device identifier, access device data from the database. The device programmer is further caused to, based upon the device data, determine an area of memory of the electronic device that can be written. The device programmer is further caused to, based on the determination of the area of memory of the electronic device that can be written, write data to the area of memory.
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20.发明申请公开(公告)号：US20220092006A1
公开(公告)日：2022-03-24
申请号：US17457185
申请日：2021-12-01
Applicant: Microchip Technology Incorporated
Inventor： Narendra Raj S V , Priyank Gupta , Michael Simmons
Abstract: Disclosed examples include an apparatus. The apparatus may include first interfaces, second interfaces, a bus interface, and a buffer interface. The first interfaces may be to communicate at first data widths via first interconnects for operable coupling with data samples sources. The second interface may be to communicate at second data widths via second interconnects for operable coupling with data sinks. The buffer interface may be to communicate with a system to process data samples sampled using different sampling rates according to processing frame durations. The buffer interface may include an uplink channel handler and a downlink channel handler. The uplink channel handler may be to receive data samples from the first interfaces at first data widths and provide the data samples to the bus interface at third data widths. The downlink channel handler may be to receive processed data samples from the bus interface at third data widths and provide the processed data samples to the second interfaces at second data widths. The bus interface to communicate at a third data width via a third interconnect for operative coupling with allocated memory region utilized by the system to process data samples.
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