公开(公告)号：US20180330766A1

公开(公告)日：2018-11-15

申请号：US15591015

申请日：2017-05-09

Applicant: Micron Technology, Inc.

Inventor： Charles Ingalls ,  Christopher Kawamura

IPC: G11C7/08 ,  G11C7/12 ,  G11C5/14

CPC classification number: G11C7/08 ,  G11C5/025 ,  G11C5/14 ,  G11C7/062 ,  G11C7/12

Abstract: Apparatuses for signal boost are disclosed An example apparatus includes: first and second digit lines coupled to memory cells; a sense amplifier including: first and second transistors having gates operatively coupled to the first digit line and drains coupled to a first node, sources of the first and second transistors coupled to first and second control lines providing first and second power supply voltage respectively; and third and fourth transistors having gates coupled to the second digit line and drains coupled to a second node, sources of the third and fourth transistors coupled to the first and second control lines respectively; a power line coupled to the first node and the second node; and a power switch providing either the first power supply voltage or a third power supply voltage smaller than the first power supply voltage to the power line.

公开(公告)号：US10902899B2

公开(公告)日：2021-01-26

申请号：US16729185

申请日：2019-12-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Kawamura

IPC: G11C8/18 ,  G11C8/10 ,  G11C7/06

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state and a sense amplifier coupled to the first digit line and to a second digit line. The sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier. The apparatus further comprising a decoder circuit coupled to the wordline and to the sense amplifier. In response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state.

公开(公告)号：US10790000B2

公开(公告)日：2020-09-29

申请号：US16191428

申请日：2018-11-14

Applicant: Micron Technology, Inc.

Inventor： Christopher Kawamura

IPC: G11C8/18 ,  G11C7/06 ,  G11C7/12 ,  G11C8/10 ,  G11C8/08

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay (tRCD) are disclosed. In some examples, tRCD may be reduced by providing a non-zero offset voltage to a target wordline at an earlier time, such as during a threshold voltage compensation phase of a sense operation. Setting the wordline to a non-zero offset voltage at an earlier time may reduce a time for the wordline to reach an activation voltage, which may reduce tRCD. In other examples, protection against row hammer attacks during precharge phases may be improved by setting the wordline to the non-zero offset voltage.

公开(公告)号：US10672435B2

公开(公告)日：2020-06-02

申请号：US16256850

申请日：2019-01-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Charles Ingalls ,  Christopher Kawamura

IPC: G11C7/00 ,  G11C7/08 ,  G11C7/12 ,  G11C5/14 ,  G11C5/02 ,  G11C7/06

Abstract: Apparatuses for signal boost are disclosed. An example apparatus includes: first and second digit lines coupled to memory cells; a sense amplifier including: first and second transistors having gates operatively coupled to the first digit line and drains coupled to a first node, sources of the first and second transistors coupled to first and second control lines providing first and second power supply voltage respectively; and third and fourth transistors having gates coupled to the second digit line and drains coupled to a second node, sources of the third and fourth transistors coupled to the first and second control lines respectively; a power line coupled to the first node and the second node; and a power switch providing either the first power supply voltage or a third power supply voltage smaller than the first power supply voltage to the power line.

公开(公告)号：US10566036B2

公开(公告)日：2020-02-18

申请号：US16009806

申请日：2018-06-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Kawamura

IPC: G11C7/12 ,  G11C5/14 ,  G11C7/08 ,  G11C7/06 ,  G11C8/10

Abstract: Apparatuses and methods for reducing sense amplifier leakage current during an active power-down are disclosed. An example apparatus includes a memory that includes a memory cell and a first digit line and a second digit line. The memory cell is coupled to the first digit line in response to activation of a wordline coupled the memory cell. The example apparatus further includes a sense amplifier comprising of a first transistor coupled between the first digit line and a first gut node of the sense amplifier and a second transistor coupled between the second digit line and a second gut node of the sense amplifier. While the wordline is activated, in response to entering a power-down mode, the first transistor is disabled to decouple the first digit line from the first gut node and the second transistor is disabled to decouple the second digit line from the second gut node.

公开(公告)号：US10522205B1

公开(公告)日：2019-12-31

申请号：US16013618

申请日：2018-06-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Kawamura

IPC: G11C8/18 ,  G11C8/10 ,  G11C7/06

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state and a sense amplifier coupled to the first digit line and to a second digit line. The sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier. The apparatus further comprising a decoder circuit coupled to the wordline and to the sense amplifier. In response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state.

公开(公告)号：US20190392877A1

公开(公告)日：2019-12-26

申请号：US16013618

申请日：2018-06-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Kawamura

IPC: G11C8/18 ,  G11C7/06 ,  G11C8/10

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state and a sense amplifier coupled to the first digit line and to a second digit line. The sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier. The apparatus further comprising a decoder circuit coupled to the wordline and to the sense amplifier. In response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state.

公开(公告)号：US20190392872A1

公开(公告)日：2019-12-26

申请号：US16017826

申请日：2018-06-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Kawamura ,  Tae H. Kim

IPC: G11C7/06 ,  G11C11/4091 ,  G11C11/4074 ,  G11C7/12 ,  G11C8/10

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state, and a sense amplifier configured to, during a sense operation, couple a first gut node to the first digit line and couple a second gut node to a second digit line in response to an isolation signal. The sense amplifier is further configured to, after the first gut node is coupled to the first digit line and the second gut node is coupled to the second digit hue, drive the first digit line to a first sense voltage of a first control signal and drive the second digit line to a second sense voltage of a second control signal based on a data state of the memory cell.

公开(公告)号：US20190147932A1

公开(公告)日：2019-05-16

申请号：US16184492

申请日：2018-11-08

Applicant: Micron Technology, Inc.

Inventor： Christopher Kawamura ,  Charles Ingalls ,  Scott Derner

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2259 ,  G11C11/2275

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. The capacitance of a digit line of the ferroelectric memory cell may be dynamically increased prior to, and during a portion of, a read operation used to determine a stored logic state of the cell. The capacitance may be increased by leveraging intrinsic capacitance of digit lines of the array—e.g., by shorting one digit line to another digit line. Increasing the capacitance of the digit line may increase the signal on the digit line that is sensed during the read operation.

公开(公告)号：US20170358340A1

公开(公告)日：2017-12-14

申请号：US15645128

申请日：2017-07-10

Applicant: Micron Technology, Inc.

Inventor： Christopher Kawamura ,  Howard Kirsch

IPC: G11C11/22

CPC classification number: G11C11/2275 ,  G11C11/1697 ,  G11C11/221 ,  G11C11/2273

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. The magnitude of a voltage applied across a ferroelectric capacitor may be dynamically increased during a write operation. For example, a memory cell may be selected for a write operation, and a voltage may be applied to a digit line corresponding to the memory cell during the write operation. An additional charge may be transferred to the digit line—e.g., from an energy storage component, such as a capacitor, that is in electronic communication with the digit line. In turn, the voltage across the ferroelectric capacitor of the memory cell may be increased.