公开(公告)号：US10074415B2

公开(公告)日：2018-09-11

申请号：US15645128

申请日：2017-07-10

Applicant: Micron Technology, Inc.

Inventor： Christopher Kawamura ,  Howard Kirsch

IPC: G11C11/22

CPC classification number: G11C11/2275 ,  G11C11/1697 ,  G11C11/221 ,  G11C11/2273

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. The magnitude of a voltage applied across a ferroelectric capacitor may be dynamically increased during a write operation. For example, a memory cell may be selected for a write operation, and a voltage may be applied to a digit line corresponding to the memory cell during the write operation. An additional charge may be transferred to the digit line—e.g., from an energy storage component, such as a capacitor, that is in electronic communication with the digit line. In turn, the voltage across the ferroelectric capacitor of the memory cell may be increased.

公开(公告)号：US20180158501A1

公开(公告)日：2018-06-07

申请号：US15858824

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Christopher Kawamura ,  Charles Ingalls ,  Scott Derner

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2259 ,  G11C11/2275

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. The capacitance of a digit line of the ferroelectric memory cell may be dynamically increased prior to, and during a portion of, a read operation used to determine a stored logic state of the cell. The capacitance may be increased by leveraging intrinsic capacitance of digit lines of the array—e.g., by shorting one digit line to another digit line. Increasing the capacitance of the digit line may increase the signal on the digit line that is sensed during the read operation.

公开(公告)号：US09934839B2

公开(公告)日：2018-04-03

申请号：US15688680

申请日：2017-08-28

Applicant: Micron Technology, Inc.

Inventor： Christopher Kawamura ,  Charles Ingalls ,  Scott Derner

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2259 ,  G11C11/2275

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. The capacitance of a digit line of the ferroelectric memory cell may be dynamically increased prior to, and during a portion of, a read operation used to determine a stored logic state of the cell. The capacitance may be increased by leveraging intrinsic capacitance of digit lines of the array—e.g., by shorting one digit line to another digit line. Increasing the capacitance of the digit line may increase the signal on the digit line that is sensed during the read operation.

公开(公告)号：US20200152249A1

公开(公告)日：2020-05-14

申请号：US16191428

申请日：2018-11-14

Applicant: Micron Technology, Inc.

Inventor： Christopher Kawamura

IPC: G11C8/18 ,  G11C7/06 ,  G11C8/08 ,  G11C8/10 ,  G11C7/12

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay (tRCD) are disclosed. In some examples, tRCD may be reduced by providing a non-zero offset voltage to a target wordline at an earlier time, such as during a threshold voltage compensation phase of a sense operation. Setting the wordline to a non-zero offset voltage at an earlier time may reduce a time for the wordline to reach an activation voltage, which may reduce tRCD. In other examples, protection against row hammer attacks during precharge phases may be improved by setting the wordline to the non-zero offset voltage.

公开(公告)号：US10541008B2

公开(公告)日：2020-01-21

申请号：US16017826

申请日：2018-06-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Kawamura ,  Tae H. Kim

IPC: G11C7/02 ,  G11C7/06 ,  G11C11/4091 ,  G11C8/10 ,  G11C7/12 ,  G11C11/4074

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state, and a sense amplifier configured to, during a sense operation, couple a first gut node to the first digit line and couple a second gut node to a second digit line in response to an isolation signal. The sense amplifier is further configured to, after the first gut node is coupled to the first digit line and the second gut node is coupled to the second digit line, drive the first digit line to a first sense voltage of a first control signal and drive the second digit line to a second sense voltage of a second control signal based on a data state of the memory cell.

公开(公告)号：US10366735B2

公开(公告)日：2019-07-30

申请号：US16102526

申请日：2018-08-13

Applicant: Micron Technology, Inc.

Inventor： Christopher Kawamura ,  Howard Kirsch

IPC: G11C11/22 ,  G11C11/16

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. The magnitude of a voltage applied across a ferroelectric capacitor may be dynamically increased during a write operation. A memory cell may be selected for a write operation, and a voltage may be applied to a digit line corresponding to the memory cell during the write operation. An additional charge may be transferred to the digit line—e.g., from an energy storage component, such as a capacitor, that is in electronic communication with the digit line. In turn, the voltage across the ferroelectric capacitor of the memory cell may be increased.

公开(公告)号：US10153024B2

公开(公告)日：2018-12-11

申请号：US15858824

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Christopher Kawamura ,  Charles Ingalls ,  Scott Derner

IPC: G11C11/22

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. The capacitance of a digit line of the ferroelectric memory cell may be dynamically increased prior to, and during a portion of, a read operation used to determine a stored logic state of the cell. The capacitance may be increased by leveraging intrinsic capacitance of digit lines of the array—e.g., by shorting one digit line to another digit line. Increasing the capacitance of the digit line may increase the signal on the digit line that is sensed during the read operation.

公开(公告)号：US11120847B2

公开(公告)日：2021-09-14

申请号：US16747824

申请日：2020-01-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Kawamura ,  Tae H. Kim

IPC: G11C7/02 ,  G11C7/06 ,  G11C11/4091 ,  G11C8/10 ,  G11C7/12 ,  G11C11/4074

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state, and a sense amplifier configured to, during a sense operation, couple a first gut node to the first digit line and couple a second gut node to a second digit line in response to an isolation signal. The sense amplifier is further configured to, after the first gut node is coupled to the first digit line and the second gut node is coupled to the second digit line, drive the first digit line to a first sense voltage of a first control signal and drive the second digit line to a second sense voltage of a second control signal based on a data state of the memory cell.

公开(公告)号：US20210027821A1

公开(公告)日：2021-01-28

申请号：US17035462

申请日：2020-09-28

Applicant: Micron Technology, Inc.

Inventor： Christopher Kawamura

IPC: G11C8/18 ,  G11C7/06 ,  G11C7/12 ,  G11C8/10 ,  G11C8/08

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay (tRCD) are disclosed. In some examples, tRCD may be reduced by providing a non-zero offset voltage to a target wordline at an earlier time, such as during a threshold voltage compensation phase of a sense operation. Setting the wordline to a non-zero offset voltage at an earlier time may reduce a time for the wordline to reach an activation voltage, which may reduce tRCD. In other examples, protection against row hammer attacks during precharge phases may be improved by setting the wordline to the non-zero offset voltage.

公开(公告)号：US20180350421A1

公开(公告)日：2018-12-06

申请号：US16102526

申请日：2018-08-13

Applicant: Micron Technology, Inc.

Inventor： Christopher Kawamura ,  Howard Kirsch

IPC: G11C11/22 ,  G11C11/16

CPC classification number: G11C11/2275 ,  G11C11/1697 ,  G11C11/221 ,  G11C11/2273

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. The magnitude of a voltage applied across a ferroelectric capacitor may be dynamically increased during a write operation. For example, a memory cell may be selected for a write operation, and a voltage may be applied to a digit line corresponding to the memory cell during the write operation. An additional charge may be transferred to the digit line—e.g., from an energy storage component, such as a capacitor, that is in electronic communication with the digit line. In turn, the voltage across the ferroelectric capacitor of the memory cell may be increased.