公开(公告)号：US10153024B2

公开(公告)日：2018-12-11

申请号：US15858824

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Christopher Kawamura ,  Charles Ingalls ,  Scott Derner

IPC: G11C11/22

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. The capacitance of a digit line of the ferroelectric memory cell may be dynamically increased prior to, and during a portion of, a read operation used to determine a stored logic state of the cell. The capacitance may be increased by leveraging intrinsic capacitance of digit lines of the array—e.g., by shorting one digit line to another digit line. Increasing the capacitance of the digit line may increase the signal on the digit line that is sensed during the read operation.

公开(公告)号：US10672435B2

公开(公告)日：2020-06-02

申请号：US16256850

申请日：2019-01-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Charles Ingalls ,  Christopher Kawamura

IPC: G11C7/00 ,  G11C7/08 ,  G11C7/12 ,  G11C5/14 ,  G11C5/02 ,  G11C7/06

Abstract: Apparatuses for signal boost are disclosed. An example apparatus includes: first and second digit lines coupled to memory cells; a sense amplifier including: first and second transistors having gates operatively coupled to the first digit line and drains coupled to a first node, sources of the first and second transistors coupled to first and second control lines providing first and second power supply voltage respectively; and third and fourth transistors having gates coupled to the second digit line and drains coupled to a second node, sources of the third and fourth transistors coupled to the first and second control lines respectively; a power line coupled to the first node and the second node; and a power switch providing either the first power supply voltage or a third power supply voltage smaller than the first power supply voltage to the power line.

公开(公告)号：US20190147932A1

公开(公告)日：2019-05-16

申请号：US16184492

申请日：2018-11-08

Applicant: Micron Technology, Inc.

Inventor： Christopher Kawamura ,  Charles Ingalls ,  Scott Derner

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2259 ,  G11C11/2275

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. The capacitance of a digit line of the ferroelectric memory cell may be dynamically increased prior to, and during a portion of, a read operation used to determine a stored logic state of the cell. The capacitance may be increased by leveraging intrinsic capacitance of digit lines of the array—e.g., by shorting one digit line to another digit line. Increasing the capacitance of the digit line may increase the signal on the digit line that is sensed during the read operation.

公开(公告)号：US20180330766A1

公开(公告)日：2018-11-15

申请号：US15591015

申请日：2017-05-09

Applicant: Micron Technology, Inc.

Inventor： Charles Ingalls ,  Christopher Kawamura

IPC: G11C7/08 ,  G11C7/12 ,  G11C5/14

CPC classification number: G11C7/08 ,  G11C5/025 ,  G11C5/14 ,  G11C7/062 ,  G11C7/12

Abstract: Apparatuses for signal boost are disclosed An example apparatus includes: first and second digit lines coupled to memory cells; a sense amplifier including: first and second transistors having gates operatively coupled to the first digit line and drains coupled to a first node, sources of the first and second transistors coupled to first and second control lines providing first and second power supply voltage respectively; and third and fourth transistors having gates coupled to the second digit line and drains coupled to a second node, sources of the third and fourth transistors coupled to the first and second control lines respectively; a power line coupled to the first node and the second node; and a power switch providing either the first power supply voltage or a third power supply voltage smaller than the first power supply voltage to the power line.

公开(公告)号：US09147473B2

公开(公告)日：2015-09-29

申请号：US13957273

申请日：2013-08-01

Applicant: Micron Technology, Inc.

Inventor： Tae Kim ,  Howard Kirsch ,  Charles Ingalls ,  K. Shawn Smith ,  Jonathan Doebler

IPC: G11C16/08 ,  G11C8/08 ,  G11C11/408 ,  G11C11/418 ,  G11C7/18 ,  G11C11/4097

CPC classification number: G11C16/08 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/4097 ,  G11C11/418

Abstract: Apparatuses, global and local wordline drivers, and methods for driving a wordline voltage in a memory is described. An example apparatus includes a memory array including a plurality of sub-arrays. The plurality of sub arrays are coupled to a wordline. The memory array further including a plurality of local wordline drivers coupled between a global wordline and the wordline. The plurality of local wordline drivers are configured to selectively couple the wordline to the global wordline during a memory access operation. The example apparatus further includes a global wordline driver configured to selectively couple the wordline to the global wordline during the memory access operation.

Abstract translation: 描述了设备，全局和本地字线驱动器以及用于驱动存储器中字线电压的方法。 示例性装置包括包括多个子阵列的存储器阵列。 多个子阵列耦合到字线。 存储器阵列还包括耦合在全局字线和字线之间的多个本地字线驱动器。 多个本地字线驱动器被配置为在存储器访问操作期间选择性地将字线耦合到全局字线。 该示例设备还包括全局字线驱动器，其被配置为在存储器访问操作期间选择性地将字线耦合到全局字线。

公开(公告)号：US20180158501A1

公开(公告)日：2018-06-07

申请号：US15858824

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Christopher Kawamura ,  Charles Ingalls ,  Scott Derner

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2259 ,  G11C11/2275

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. The capacitance of a digit line of the ferroelectric memory cell may be dynamically increased prior to, and during a portion of, a read operation used to determine a stored logic state of the cell. The capacitance may be increased by leveraging intrinsic capacitance of digit lines of the array—e.g., by shorting one digit line to another digit line. Increasing the capacitance of the digit line may increase the signal on the digit line that is sensed during the read operation.

公开(公告)号：US09934839B2

公开(公告)日：2018-04-03

申请号：US15688680

申请日：2017-08-28

Applicant: Micron Technology, Inc.

Inventor： Christopher Kawamura ,  Charles Ingalls ,  Scott Derner

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2259 ,  G11C11/2275

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. The capacitance of a digit line of the ferroelectric memory cell may be dynamically increased prior to, and during a portion of, a read operation used to determine a stored logic state of the cell. The capacitance may be increased by leveraging intrinsic capacitance of digit lines of the array—e.g., by shorting one digit line to another digit line. Increasing the capacitance of the digit line may increase the signal on the digit line that is sensed during the read operation.

公开(公告)号：US20150036442A1

公开(公告)日：2015-02-05

申请号：US13957273

申请日：2013-08-01

Applicant: Micron Technology, Inc.

Inventor： Tae Kim ,  Howard Kirsch ,  Charles Ingalls ,  K. Shawn Smith ,  Jonathan Doebler

IPC: G11C7/12

CPC classification number: G11C16/08 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/4097 ,  G11C11/418

Abstract: Apparatuses, global and local wordline drivers, and methods for driving a wordline voltage in a memory is described. An example apparatus includes a memory array including a plurality of sub-arrays. The plurality of sub arrays are coupled to a wordline. The memory array further including a plurality of local wordline drivers coupled between a global wordline and the wordline. The plurality of local wordline drivers are configured to selectively couple the wordline to the global wordline during a memory access operation. The example apparatus further includes a global wordline driver configured to selectively couple the wordline to the global wordline during the memory access operation.

Abstract translation: 描述了设备，全局和本地字线驱动器以及用于驱动存储器中字线电压的方法。 示例性装置包括包括多个子阵列的存储器阵列。 多个子阵列耦合到字线。 存储器阵列还包括耦合在全局字线和字线之间的多个本地字线驱动器。 多个本地字线驱动器被配置为在存储器访问操作期间选择性地将字线耦合到全局字线。 该示例设备还包括全局字线驱动器，其被配置为在存储器访问操作期间选择性地将字线耦合到全局字线。

公开(公告)号：US10796743B2

公开(公告)日：2020-10-06

申请号：US16184492

申请日：2018-11-08

Applicant: Micron Technology, Inc.

Inventor： Christopher Kawamura ,  Charles Ingalls ,  Scott Derner

IPC: G11C11/22

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. The capacitance of a digit line of the ferroelectric memory cell may be dynamically increased prior to, and during a portion of, a read operation used to determine a stored logic state of the cell. The capacitance may be increased by leveraging intrinsic capacitance of digit lines of the array—e.g., by shorting one digit line to another digit line. Increasing the capacitance of the digit line may increase the signal on the digit line that is sensed during the read operation.

公开(公告)号：US20190156869A1

公开(公告)日：2019-05-23

申请号：US16256850

申请日：2019-01-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Charles Ingalls ,  Christopher Kawamura

IPC: G11C7/08 ,  G11C7/06 ,  G11C7/12 ,  G11C5/14 ,  G11C5/02

Abstract: Apparatuses for signal boost are disclosed. An example apparatus includes: first and second digit lines coupled to memory cells; a sense amplifier including: first and second transistors having gates operatively coupled to the first digit line and drains coupled to a first node, sources of the first and second transistors coupled to first and second control lines providing first and second power supply voltage respectively; and third and fourth transistors having gates coupled to the second digit line and drains coupled to a second node, sources of the third and fourth transistors coupled to the first and second control lines respectively; a power line coupled to the first node and the second node; and a power switch providing either the first power supply voltage or a third power supply voltage smaller than the first power supply voltage to the power line.