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公开(公告)号：US10783965B2
公开(公告)日：2020-09-22
申请号：US16399144
申请日：2019-04-30
Applicant: Micron Technology, Inc.
Inventor： DerChang Kau , Gianpaolo Spadini
Abstract: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
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公开(公告)号：US10431270B2
公开(公告)日：2019-10-01
申请号：US15859029
申请日：2017-12-29
Applicant: Micron Technology, Inc.
Inventor： Davide Mantegazza , Kiran Pangal , Feng Q. Pan , Hernan A. Castro , DerChang Kau
Abstract: Apparatuses for increasing the voltage budget window of a memory array are described. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.
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公开(公告)号：US20190259453A1
公开(公告)日：2019-08-22
申请号：US16399144
申请日：2019-04-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： DerChang Kau , Gianpaolo Spadini
Abstract: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
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公开(公告)号：US10304534B2
公开(公告)日：2019-05-28
申请号：US16198347
申请日：2018-11-21
Applicant: Micron Technology, Inc.
Inventor： DerChang Kau , Gianpaolo Spadini
Abstract: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
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公开(公告)号：US09653127B1
公开(公告)日：2017-05-16
申请号：US14970380
申请日：2015-12-15
Applicant: Micron Technology, Inc.
Inventor： Davide Mantegazza , Kiran Pangal , Feng Q. Pan , Hernan A. Castro , DerChang Kau
IPC: G11C5/14
CPC classification number: G11C7/22 , G11C5/147 , G11C7/1063 , G11C13/0004 , G11C13/0023 , G11C13/0033 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C2013/0092 , G11C2213/71
Abstract: Methods and apparatuses for increasing the voltage budget window of a memory array are disclosed. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.
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Patent Agency Ranking
16.发明授权公开(公告)号：US09368554B2
公开(公告)日：2016-06-14
申请号：US14973446
申请日：2015-12-17
Applicant: Micron Technology, Inc.
Inventor： DerChang Kau , Gianpaolo Spadini
IPC: G11C11/00 , H01L27/24 , H01L45/00 , H01L23/528
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0097 , G11C16/08 , G11C16/24 , H01L23/528 , H01L27/2427 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144 , H01L2924/0002 , H01L2924/00
Abstract: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
Abstract translation: 一些实施例包括具有存储器单元，被配置为访问存储单元的第一和第二导线以及被配置为向第一和第二导线中的一个施加信号的开关的装置和方法。 在这样的实施例中的至少一个中，开关可以包括相变材料。 描述包括附加装置和方法的其他实施例。
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公开(公告)号：US10163507B1
公开(公告)日：2018-12-25
申请号：US16111746
申请日：2018-08-24
Applicant: Micron Technology, Inc.
Inventor： DerChang Kau , Gianpaolo Spadini
Abstract: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
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公开(公告)号：US10090050B2
公开(公告)日：2018-10-02
申请号：US15905317
申请日：2018-02-26
Applicant: Micron Technology, Inc.
Inventor： DerChang Kau , Gianpaolo Spadini
Abstract: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
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公开(公告)号：US20180151206A1
公开(公告)日：2018-05-31
申请号：US15859029
申请日：2017-12-29
Applicant: Micron Technology, Inc.
Inventor： Davide Mantegazza , Kiran Pangal , Feng Q. Pan , Hernan A. Castro , DerChang Kau
CPC classification number: G11C7/22 , G11C5/147 , G11C7/1063 , G11C13/0004 , G11C13/0023 , G11C13/0033 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C2013/0092 , G11C2213/71
Abstract: Apparatuses for increasing the voltage budget window of a memory array are described. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.
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公开(公告)号：US09905280B2
公开(公告)日：2018-02-27
申请号：US15490327
申请日：2017-04-18
Applicant: Micron Technology, Inc.
Inventor： Davide Mantegazza , Kiran Pangal , Feng Q. Pan , Hernan A. Castro , DerChang Kau
CPC classification number: G11C7/22 , G11C5/147 , G11C7/1063 , G11C13/0004 , G11C13/0023 , G11C13/0033 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C2013/0092 , G11C2213/71
Abstract: Methods and apparatuses for increasing the voltage budget window of a memory array are disclosed. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.
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