公开(公告)号：US10365835B2

公开(公告)日：2019-07-30

申请号：US14288663

申请日：2014-05-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Domenico Monteleone ,  Giacomo Bernardi ,  Luca Porzio ,  Graziano Mirichigni ,  Stefano Zanardi ,  Erminio Di Martino

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

Abstract: Apparatuses and methods for commands to perform wear leveling operations are described herein. An example apparatus may include a memory configured to receive a wear leveling command and to perform a wear leveling operation responsive to the wear leveling command. The memory may further be configured to recommend a wear leveling command be provided to the memory responsive to a global write count exceeding a threshold. The global write count may be indicative of a number of write operations performed by the memory since the memory performed a wear leveling operation.

公开(公告)号：US20170300413A1

公开(公告)日：2017-10-19

申请号：US15637961

申请日：2017-06-29

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Luca Porzio ,  Erminio Di Martino ,  Giacomo Bernardi ,  Domenico Monteleone ,  Stefano Zanardi ,  Chee Weng Tan ,  Sebastien LeMarie ,  Andre Klindworth

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F12/0891 ,  G06F13/00 ,  G06F13/1673 ,  G06F13/1694 ,  G06F2212/1024

Abstract: Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.

公开(公告)号：US09727493B2

公开(公告)日：2017-08-08

申请号：US13967206

申请日：2013-08-14

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Luca Porzio ,  Erminio Di Martino ,  Giacomo Bernardi ,  Domenico Monteleone ,  Stefano Zanardi ,  Chee Weng Tan ,  Sebastien LeMarie ,  Andre Klindworth

IPC: G06F13/00 ,  G06F13/16 ,  G06F12/08 ,  G06F12/0891

CPC classification number: G06F12/0804 ,  G06F12/0891 ,  G06F13/00 ,  G06F13/1673 ,  G06F13/1694 ,  G06F2212/1024

Abstract: Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.

公开(公告)号：US20150052299A1

公开(公告)日：2015-02-19

申请号：US13967206

申请日：2013-08-14

Applicant: Micron Technology, Inc.

Inventor： GRAZIANO MIRICHIGNI ,  Luca Porzio ,  Erminio Di Martino ,  Giacomo Bernardi ,  Domenico Monteleone ,  Stefano Zanardi ,  Chee Weng Tan ,  Sebastien LeMarie ,  Andre Klindworth

IPC: G06F3/06

CPC classification number: G06F12/0804 ,  G06F12/0891 ,  G06F13/00 ,  G06F13/1673 ,  G06F13/1694 ,  G06F2212/1024

Abstract: Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.

Abstract translation: 本文公开了用于向可配置存储区域提供数据的设备和方法。 示例性装置可以包括至少部分地基于多个配置的扩展地址寄存器，其包括指示偏移和大小的多个配置位，具有存储区域的阵列，存储区域的大小和偏移量 位和被配置为存储数据的缓冲器，所述数据包括旨在存储在存储区域中的数据。 存储器控制单元可以耦合到缓冲器并且被配置为使得缓冲器至少部分地响应于冲洗命令来将要存储在阵列的存储区域中的数据存储在阵列的存储区域中。

公开(公告)号：US20240345925A1

公开(公告)日：2024-10-17

申请号：US18638245

申请日：2024-04-17

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Ferdinando Pascale ,  Roberto Izzi ,  Marco Onorato ,  Erminio Di Martino

IPC: G06F11/14 ,  G06F1/24 ,  G06F9/4401

CPC classification number: G06F11/1417 ,  G06F1/24 ,  G06F9/4405

Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

公开(公告)号：US11347402B2

公开(公告)日：2022-05-31

申请号：US16523860

申请日：2019-07-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Domenico Monteleone ,  Giacomo Bernardi ,  Luca Porzio ,  Graziano Mirichigni ,  Stefano Zanardi ,  Erminio Di Martino

IPC: G06F3/06 ,  G06F12/02

Abstract: Apparatuses and methods for commands to perform wear leveling operations are described herein. An example apparatus may include a memory configured to receive a wear leveling command and to perform a wear leveling operation responsive to the wear leveling command. The memory may further be configured to recommend a wear leveling command be provided to the memory responsive to a global write count exceeding a threshold. The global write count may be indicative of a number of write operations performed by the memory since the memory performed a wear leveling operation.

公开(公告)号：US20210286516A1

公开(公告)日：2021-09-16

申请号：US17331281

申请日：2021-05-26

Applicant: Micron Technology, Inc.

Inventor： Claudio Giaccio ,  Erminio Di Martino ,  Jeffery Carlos Bell

IPC: G06F3/06 ,  G06F11/10

Abstract: Devices and techniques are disclosed herein to extend a range of an effective delay of a delay circuit having a configurable delay limited to a first range of delay values with respect to a first edge of a clock signal. A selection circuit can selectively apply the configurable delay to a subsequent, second edge of the clock signal to extend the range of the effective delay of the delay circuit beyond the first range of delay values.

公开(公告)号：US11061431B2

公开(公告)日：2021-07-13

申请号：US16022307

申请日：2018-06-28

Applicant: Micron Technology, Inc.

Inventor： Claudio Giaccio ,  Ferdinando Pascale ,  Erminio Di Martino ,  Raffaele Mastrangelo ,  Ferdinando D'Alessandro ,  Andrea Castaldo ,  Cristiano Castellano

IPC: G06F1/12

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

公开(公告)号：US20190171567A1

公开(公告)日：2019-06-06

申请号：US16272945

申请日：2019-02-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Luca Porzio ,  Erminio Di Martino ,  Giacomo Bernardi ,  Domenico Monteleone ,  Stefano Zanardi ,  Chee Weng Tan ,  Sebastien LeMarie ,  Andre Klindworth

IPC: G06F12/0804 ,  G06F13/00 ,  G06F13/16 ,  G06F12/0891

Abstract: Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus mau include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.

公开(公告)号：US09710192B2

公开(公告)日：2017-07-18

申请号：US15367631

申请日：2016-12-02

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Luca Porzio ,  Erminio Di Martino ,  Giacomo Bernardi ,  Domenico Monteleone ,  Stefano Zanardi

IPC: G06F3/06 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0891

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0804 ,  G06F12/0891 ,  G06F2212/7203

Abstract: Apparatuses and methods for providing data from a buffer are disclosed herein. An example apparatus may include an array, a buffer, and a memory control unit. The buffer may be coupled to the array and configured to store data. The memory control unit may be coupled to the array and the buffer. The memory control unit may be configured to cause the buffer to store the data responsive, at least in part, to a first write command and may further be configured to cause the buffer to store the data in the array responsive, at least in part, to a flush command. The memory control unit may further be configured to interrupt the flush command to prepare for a read command or a second write command and resume the flush command once the read command or the second write command is performed.