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    Apparatuses and methods for memory operations having variable latencies
    1.
    发明授权
    Apparatuses and methods for memory operations having variable latencies 有权

    公开(公告)号：US10915321B2

    公开(公告)日：2021-02-09

    申请号：US16105846

    申请日：2018-08-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio ,  Chee Weng Tan ,  Sebastien Lemarie ,  Andre Klindworth

    IPC: G06F9/30 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C13/00

    Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.

    APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES
    7.
    发明申请
    APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES 审中-公开

    公开(公告)号：US20190012173A1

    公开(公告)日：2019-01-10

    申请号：US16105846

    申请日：2018-08-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio ,  Chee Weng Tan ,  Sebastien Lemarie ,  Andre Kindworth

    IPC: G06F9/30 ,  G11C13/00 ,  G06F13/16 ,  G11C7/22 ,  G11C7/10

    Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.

    APPARATUSES AND METHODS FOR PROVIDING DATA TO A CONFIGURABLE STORAGE AREA
    10.
    发明申请
    APPARATUSES AND METHODS FOR PROVIDING DATA TO A CONFIGURABLE STORAGE AREA 有权
    用于向可配置存储区域提供数据的设备和方法

    公开(公告)号：US20150052299A1

    公开(公告)日：2015-02-19

    申请号：US13967206

    申请日：2013-08-14

    Applicant: Micron Technology, Inc.

    Inventor： GRAZIANO MIRICHIGNI ,  Luca Porzio ,  Erminio Di Martino ,  Giacomo Bernardi ,  Domenico Monteleone ,  Stefano Zanardi ,  Chee Weng Tan ,  Sebastien LeMarie ,  Andre Klindworth

    IPC: G06F3/06

    CPC classification number: G06F12/0804 ,  G06F12/0891 ,  G06F13/00 ,  G06F13/1673 ,  G06F13/1694 ,  G06F2212/1024

    Abstract: Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.

    Abstract translation: 本文公开了用于向可配置存储区域提供数据的设备和方法。 示例性装置可以包括至少部分地基于多个配置的扩展地址寄存器，其包括指示偏移和大小的多个配置位，具有存储区域的阵列，存储区域的大小和偏移量 位和被配置为存储数据的缓冲器，所述数据包括旨在存储在存储区域中的数据。 存储器控制单元可以耦合到缓冲器并且被配置为使得缓冲器至少部分地响应于冲洗命令来将要存储在阵列的存储区域中的数据存储在阵列的存储区域中。

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