公开(公告)号：US11257529B2

公开(公告)日：2022-02-22

申请号：US17100368

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Yangsung Joo ,  Hidekazu Noguchi

IPC: G11C7/22 ,  G11C7/04 ,  G11C7/12 ,  G11C11/4076 ,  H03K5/13 ,  G11C11/408 ,  H03K5/00

Abstract: Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the inning for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.

公开(公告)号：US12131767B2

公开(公告)日：2024-10-29

申请号：US17929981

申请日：2022-09-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hidekazu Noguchi

IPC: G11C11/406

CPC classification number: G11C11/40611

Abstract: Apparatuses and methods for calculating targeted refresh addresses may include circuitry that may be used to calculate victim row addresses having a variety of spatial relationships to an aggressor row. The spatial relationship of the victim row addresses calculated by the circuitry may be based, at least in part, on states of control signals provided to the circuitry. That is, the circuitry may be used to calculate the different victim row addresses by changing the states of the control signals.

公开(公告)号：US11468937B2

公开(公告)日：2022-10-11

申请号：US17093334

申请日：2020-11-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hidekazu Noguchi

IPC: G11C11/406

Abstract: Apparatuses and methods for calculating targeted refresh addresses may include circuitry that may be used to calculate victim row addresses having a variety of spatial relationships to an aggressor row. The spatial relationship of the victim row addresses calculated by the circuitry may be based, at least in part, on states of control signals provided to the circuitry. That is, the circuitry may be used to calculate the different victim row addresses by changing the states of the control signals.

公开(公告)号：US11450378B2

公开(公告)日：2022-09-20

申请号：US17037467

申请日：2020-09-29

Applicant: Micron Technology, Inc.

Inventor： Toshiyuki Sato ,  Hidekazu Noguchi

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/406 ,  G11C11/4076

Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as a first transistor having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and at third node; a plurality of transistors coupled to the second node and further configured to receive a power supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and further provides the plurality of signals indicative of a second drive strength in a second memory operation.

公开(公告)号：US20220101910A1

公开(公告)日：2022-03-31

申请号：US17037467

申请日：2020-09-29

Applicant: Micron Technology, Inc.

Inventor： Toshiyuki Sato ,  Hidekazu Noguchi

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/406 ,  G11C11/408

Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as a first transistor having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and at third node; a plurality of transistors coupled to the second node and further configured to receive a power supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and further provides the plurality of signals indicative of a second drive strength in a second memory operation.

公开(公告)号：US20210166752A1

公开(公告)日：2021-06-03

申请号：US17175485

申请日：2021-02-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hidekazu Noguchi

IPC: G11C11/406

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for distributed timing of targeted refresh operations. Information stored in volatile memory cells may decay unless refresh operations are performed. A memory device may perform auto-refresh operations, as well as one or more types of targeted refresh operations, where particular rows are targeted for a refresh. Targeted refresh operations may draw less power than an auto-refresh operation. It may be desirable to distribute targeted refresh operations throughout a sequence of refresh operations, to average out a power draw in the memory device. Responsive to an activation of a refresh signal, the memory device may perform a group of refresh operations. At least one refresh operation in each group may be a targeted refresh operation.

公开(公告)号：US10957377B2

公开(公告)日：2021-03-23

申请号：US16232837

申请日：2018-12-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hidekazu Noguchi

IPC: G11C7/00 ,  G11C11/406

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for distributed timing of targeted refresh operations. Information stored in volatile memory cells may decay unless refresh operations are performed. A memory device may perform auto-refresh operations, as well as one or more types of targeted refresh operations, where particular rows are targeted for a refresh. Targeted refresh operations may draw less power than an auto-refresh operation. It may be desirable to distribute targeted refresh operations throughout a sequence of refresh operations, to average out a power draw in the memory device. Responsive to an activation of a refresh signal, the memory device may perform a group of refresh operations. At least one refresh operation in each group may be a targeted refresh operation.

公开(公告)号：US20210075408A1

公开(公告)日：2021-03-11

申请号：US16563334

申请日：2019-09-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hidekazu Noguchi

IPC: H03K3/84 ,  G11C11/406

Abstract: Disclosed herein is an apparatus that includes a first circuit configured to generate a first signal a first number of times in response to an input signal, a second circuit configured to generate a second signal having a second numerical value each time the first signal is activated, and a third circuit configured to receive the second signal to update a count value obtained by accumulating the second numerical value, configured to generate a third signal each time the count value reaches a third numerical value, and configured to update the count value obtained by accumulating the second numerical value and subtracting the third numerical value when the count value reached the third numerical value.

公开(公告)号：US10580475B2

公开(公告)日：2020-03-03

申请号：US15876566

申请日：2018-01-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Masaru Morohashi ,  Hidekazu Noguchi

IPC: G06F13/00 ,  G11C11/406 ,  G11C15/04 ,  G11C8/10 ,  G06F13/16 ,  G11C16/34

Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.

公开(公告)号：US11322192B2

公开(公告)日：2022-05-03

申请号：US16805197

申请日：2020-02-28

Applicant: Micron Technology, Inc.

Inventor： Masaru Morohashi ,  Hidekazu Noguchi

IPC: G06F13/00 ,  G11C11/406 ,  G11C15/04 ,  G11C8/10 ,  G06F13/16 ,  G11C16/34

Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.