-
公开(公告)号：US11322209B2
公开(公告)日：2022-05-03
申请号：US17321569
申请日：2021-05-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michele Piccardi , Kalyan C. Kavalipurapu , Xiaojiang Guo
Abstract: A memory device includes a memory array comprising a plurality of planes, a plurality of voltage generation systems, and a controller. Each voltage generation system is electrically coupled to a corresponding plane. The controller is configured to turn on and warm up each voltage generation system of the plurality of voltage generation systems in response to a first command to access any plane of the plurality of planes and turn off and slowly discharge each voltage generation system of the plurality of voltage generation systems into an idle state in response to no commands being processed. In response to receiving a subsequent command to access any plane of the plurality of planes prior to the voltage generation systems reaching the idle state, a warm up period of the plurality of voltage generation systems is reduced.
-
Patent Agency Ranking
公开(公告)号：US20210241832A1
公开(公告)日：2021-08-05
申请号：US17238482
申请日：2021-04-23
Applicant: Micron Technology, Inc.
Inventor： Allahyar Vahidimowlavi , Kalyan C. Kavalipurapu
Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) upon the selected wordline reaching the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.
-
公开(公告)号：US11037636B2
公开(公告)日：2021-06-15
申请号：US17016946
申请日：2020-09-10
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michele Piccardi , Kalyan C. Kavalipurapu , Xiaojiang Guo
Abstract: A memory device includes a memory array comprising a plurality of planes, a plurality of voltage generation systems, and a controller. Each voltage generation system of the plurality of voltage generation systems is electrically coupled to a corresponding plane of the plurality of planes. The controller is configured to turn on each voltage generation system of the plurality of voltage generation systems in response to a first command to access a first plane of the plurality of planes. The controller is configured to operate the voltage generation system of the plurality of voltage generation systems corresponding to the first plane of the plurality of planes at a first clock frequency, and operate the remaining voltage generation systems of the plurality of voltage generation systems corresponding to the other planes of the plurality of planes at a second clock frequency less than the first clock frequency.
-
14.发明申请公开(公告)号：US20200185033A1
公开(公告)日：2020-06-11
申请号：US16752981
申请日：2020-01-27
Applicant: Micron Technology, Inc.
Inventor： Allahyar Vahidimowlavi , Kalyan C. Kavalipurapu
Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) when the selected wordline reaches the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.
-
公开(公告)号：US09947418B2
公开(公告)日：2018-04-17
申请号：US15096439
申请日：2016-04-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Mark A. Helm , Kalyan C. Kavalipurapu
CPC classification number: G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/10
Abstract: Methods of operating a memory include generating a programming pulse for a programming operation having a plurality of steps prior to a program voltage level of the programming pulse, and generating a subsequent programming pulse for the programming operation having the plurality of steps prior to a program voltage level of the subsequent programming pulse, wherein a particular step of the plurality of steps of the programming pulse has a different magnitude than a corresponding step of the plurality of steps of the subsequent programming pulse.
-
公开(公告)号：US20170294233A1
公开(公告)日：2017-10-12
申请号：US15096439
申请日：2016-04-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Mark A. Helm , Kalyan C. Kavalipurapu
CPC classification number: G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/10
Abstract: Methods of operating a memory include generating a programming pulse for a programming operation having a plurality of steps prior to a program voltage level of the programming pulse, and generating a subsequent programming pulse for the programming operation having the plurality of steps prior to a program voltage level of the subsequent programming pulse, wherein a particular step of the plurality of steps of the programming pulse has a different magnitude than a corresponding step of the plurality of steps of the subsequent programming pulse.
-
-
-
-
-
Search Results
16
records
(took 0.015 seconds)
