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公开(公告)号：US20210104284A1
公开(公告)日：2021-04-08
申请号：US17123396
申请日：2020-12-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kalyan C. Kavalipurapu , Xiaojiang Guo
Abstract: Memories including an array of memory cells, a local access line connected to a plurality of memory cells of the array of memory cells, a global access line, a transistor connected between the global access line and the local access line, and an energy store either selectively connected to a control gate of the transistor, or selectively connected to a control gate of a different transistor connected between the control gate of the transistor and a voltage node configured to receive a reference potential.
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公开(公告)号：US10546641B1
公开(公告)日：2020-01-28
申请号：US16214007
申请日：2018-12-07
Applicant: Micron Technology, Inc.
Inventor： Allahyar Vahidimowlavi , Kalyan C. Kavalipurapu
Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) when the selected wordline reaches the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.
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公开(公告)号：US11205492B2
公开(公告)日：2021-12-21
申请号：US17123396
申请日：2020-12-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kalyan C. Kavalipurapu , Xiaojiang Guo
Abstract: Memories including an array of memory cells, a local access line connected to a plurality of memory cells of the array of memory cells, a global access line, a transistor connected between the global access line and the local access line, and an energy store either selectively connected to a control gate of the transistor, or selectively connected to a control gate of a different transistor connected between the control gate of the transistor and a voltage node configured to receive a reference potential.
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公开(公告)号：US20180308551A1
公开(公告)日：2018-10-25
申请号：US15928856
申请日：2018-03-22
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Mark A. Helm , Kalyan C. Kavalipurapu
CPC classification number: G11C16/10 , G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/3459
Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.
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公开(公告)号：US11183247B2
公开(公告)日：2021-11-23
申请号：US16546417
申请日：2019-08-21
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Mark A. Helm , Kalyan C. Kavalipurapu
Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.
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Patent Agency Ranking
公开(公告)号：US20210272635A1
公开(公告)日：2021-09-02
申请号：US17321569
申请日：2021-05-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michele Piccardi , Kalyan C. Kavalipurapu , Xiaojiang Guo
Abstract: A memory device includes a memory array comprising a plurality of planes, a plurality of voltage generation systems, and a controller. Each voltage generation system is electrically coupled to a corresponding plane. The controller is configured to turn on and warm up each voltage generation system of the plurality of voltage generation systems in response to a first command to access any plane of the plurality of planes and turn off and slowly discharge each voltage generation system of the plurality of voltage generation systems into an idle state in response to no commands being processed. In response to receiving a subsequent command to access any plane of the plurality of planes prior to the voltage generation systems reaching the idle state, a warm up period of the plurality of voltage generation systems is reduced.
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公开(公告)号：US11004513B2
公开(公告)日：2021-05-11
申请号：US16752981
申请日：2020-01-27
Applicant: Micron Technology, Inc.
Inventor： Allahyar Vahidimowlavi , Kalyan C. Kavalipurapu
Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) when the selected wordline reaches the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.
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公开(公告)号：US10892022B1
公开(公告)日：2021-01-12
申请号：US16553449
申请日：2019-08-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kalyan C. Kavalipurapu , Xiaojiang Guo
Abstract: Methods of operating a memory, and memories configured to perform similar methods, might include initiating discharge of a global access line that is connected to a local access line through a transistor, and electrically floating a control gate of the transistor, in response to a supply voltage decreasing to a first threshold, and initiating discharge of the control gate of the transistor in response to the supply voltage decreasing to a second threshold lower than the first threshold.
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公开(公告)号：US10796773B1
公开(公告)日：2020-10-06
申请号：US16411210
申请日：2019-05-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michele Piccardi , Kalyan C. Kavalipurapu , Xiaojiang Guo
Abstract: A memory device includes a memory array, a plurality of voltage generation systems, and a controller. The memory array includes a plurality of planes. Each voltage generation system of the plurality of voltage generation systems is electrically coupled to a corresponding plane of the plurality of planes. The controller is configured to turn on each voltage generation system of the plurality of voltage generation systems in response to a first command to access a first plane of the plurality of planes.
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公开(公告)号：US10431310B2
公开(公告)日：2019-10-01
申请号：US15928856
申请日：2018-03-22
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Mark A. Helm , Kalyan C. Kavalipurapu
Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.
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