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    Multi-layer code rate architecture for copyback between partitions with different code rates
    3.
    发明授权
    Multi-layer code rate architecture for copyback between partitions with different code rates 有权

    公开(公告)号：US11829245B2

    公开(公告)日：2023-11-28

    申请号：US17696245

    申请日：2022-03-16

    Applicant: Micron Technology, Inc.

    Inventor： Mustafa N. Kaynak ,  Kishore Kumar Muchherla ,  Sivagnanam Parthasarathy ,  James Fitzpatrick ,  Mark A. Helm

    IPC: G06F11/10 ,  H03M13/29

    CPC classification number: G06F11/1068 ,  H03M13/2906

    Abstract: Systems, methods, and apparatus related to a multi-level error correction architecture used for copying data in memory devices. In one approach, user data is stored in the first partition of a non-volatile memory. First error correction code data is generated for the user data and stored with the user data in the first partition. Second error correction code data is generated for the user data and stored outside the first partition. The second error correction code data provides an increased error correcting capability that is compatible with the error correction algorithm used with the first error correction code data. A copyback operation is used to copy the user data and the first error correction code, but not the second error correction code, to a second partition of the non-volatile memory. The second error correction code can be selectively used if there is a need to recover portions of the user data stored in the first partition.

    IMPLEMENTING VARIABLE NUMBER OF BITS PER CELL ON STORAGE DEVICES
    4.
    发明公开
    IMPLEMENTING VARIABLE NUMBER OF BITS PER CELL ON STORAGE DEVICES 审中-公开

    公开(公告)号：US20230205463A1

    公开(公告)日：2023-06-29

    申请号：US18116526

    申请日：2023-03-02

    Applicant: Micron Technology, Inc.

    Inventor： Mark A. Helm

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0673 ,  G06F3/0653 ,  G06F3/0611

    Abstract: Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations including programming first data to a set of memory cells of a first wordline using a first number of bits per memory cell. Responsive to receiving second data to program to the set of memory cells of the first wordline, the operations further include determining an error rate associated with a second wordline adjacent to the first wordline. Responsive to determining that the error rate satisfies a threshold criterion, the operations further include selecting a second number of bits per memory cell to program the second data to the first wordline and reprograming, using the second number of bits per memory cell, the first wordline storing the first data by programming second data to the set of memory cells while maintaining the first data.

    IMPLEMENTING FAULT TOLERANT PAGE STRIPES ON LOW DENSITY MEMORY SYSTEMS
    6.
    发明申请
    IMPLEMENTING FAULT TOLERANT PAGE STRIPES ON LOW DENSITY MEMORY SYSTEMS 有权

    公开(公告)号：US20220357873A1

    公开(公告)日：2022-11-10

    申请号：US17872206

    申请日：2022-07-25

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Mark A. Helm ,  Giuseppina Puzzilli ,  Peter Feeley ,  Yifen Liu ,  Violante Moschiano ,  Akira Goda ,  Sampath K. Ratnam

    IPC: G06F3/06

    Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.

    SEPARATE PARTITION FOR BUFFER AND SNAPSHOT MEMORY
    7.
    发明申请
    SEPARATE PARTITION FOR BUFFER AND SNAPSHOT MEMORY 有权

    公开(公告)号：US20220350517A1

    公开(公告)日：2022-11-03

    申请号：US17846462

    申请日：2022-06-22

    Applicant: Micron Technology, Inc.

    Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, JR. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

    IPC: G06F3/06

    Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.

    Implementing fault tolerant page stripes on low density memory systems
    8.
    发明授权
    Implementing fault tolerant page stripes on low density memory systems 有权

    公开(公告)号：US11449271B2

    公开(公告)日：2022-09-20

    申请号：US17079048

    申请日：2020-10-23

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Mark A. Helm ,  Giuseppina Puzzilli ,  Peter Feeley ,  Yifen Liu ,  Violante Moschiano ,  Akira Goda ,  Sampath K. Ratnam

    IPC: G06F3/06

    Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.

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