公开(公告)号：US10535387B2

公开(公告)日：2020-01-14

申请号：US15891353

申请日：2018-02-07

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen

IPC: G11C7/00 ,  G11C8/18 ,  G11C7/10 ,  G06F5/06 ,  G06F13/42 ,  G11C29/50 ,  G06F13/16

Abstract: Memory devices and methods include receiving data at an input buffer and outputting serial data. The serial shift data is passed toward a serial shift register that shifts its stored data into a data write bus in a parallel format. Serial shift register loading circuitry controls loading of a serial shift register. The serial shift register loading circuitry is configured to receive a data strobe signal and provide the data strobe to the serial shift register to cause the serial shift register to shift in the serial data during a write operation. The serial register loading circuitry includes gating circuitry that is configured to cutoff provision of the data strobe from the serial register loading circuitry based at least in part on a load signal that indicates that the data write bus has been loaded with the serial data in a parallel format.

公开(公告)号：US12183385B2

公开(公告)日：2024-12-31

申请号：US17890974

申请日：2022-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William C. Waldrop ,  Liang Chen ,  Shingo Mitsubori ,  Ryo Fujimaki ,  Atsuko Momma

IPC: G11C11/4096 ,  G11C11/4076

Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

公开(公告)号：US20240062803A1

公开(公告)日：2024-02-22

申请号：US17890974

申请日：2022-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William C. Waldrop ,  Liang Chen ,  Shingo Mitsubori ,  Ryo Fujimaki ,  Atsuko Momma

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C11/4096

Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

公开(公告)号：US11675541B2

公开(公告)日：2023-06-13

申请号：US17506472

申请日：2021-10-20

Applicant: Micron Technology, Inc.

Inventor： Liang Chen

IPC: G06F3/06 ,  G11C11/409 ,  G11C11/4093

CPC classification number: G06F3/0659 ,  G11C11/409 ,  G11C11/4093

Abstract: A memory device includes a command interface configured to receive a command from a host device via multiple command address bits. The memory device also includes a centralized command decoder configured to receive the command and to determine whether the command matches a bit pattern corresponding to multiple command types, such as a write command and a read command. The centralized command decoder is also configured to, in response to the command matching the bit pattern, asserting a latch signal. The memory device also includes a latch configured to capture the multiple command address bits based at least in part on assertion of the latch signal.

公开(公告)号：US20230124182A1

公开(公告)日：2023-04-20

申请号：US17506472

申请日：2021-10-20

Applicant: Micron Technology, Inc.

Inventor： Liang Chen

IPC: G06F3/06

Abstract: A memory device includes a command interface configured to receive a command from a host device via multiple command address bits. The memory device also includes a centralized command decoder configured to receive the command and to determine whether the command matches a bit pattern corresponding to multiple command types, such as a write command and a read command. The centralized command decoder is also configured to, in response to the command matching the bit pattern, asserting a latch signal. The memory device also includes a latch configured to capture the multiple command address bits based at least in part on assertion of the latch signal.

公开(公告)号：US20220180918A1

公开(公告)日：2022-06-09

申请号：US17116634

申请日：2020-12-09

Applicant: Micron Technology, Inc.

Inventor： Liang Chen

IPC: G11C11/4096 ,  G11C11/4076 ,  G06F3/06

Abstract: A host device and memory device perform internal write leveling of a data strobe with a write command. The memory device includes an input-output interface that receives the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal. The internal write circuitry includes an emulation loop configured to emulate circuitry in a clock path of a write clock generated from the clock and used to generate a feedback clock. The internal write circuitry includes a write delay lock loop configured to receive the write clock and the feedback clock to determine a number of cycles used for the loop, transmit the number of cycles to the host device to be used as a cycle adjust in an internal write leveling process, and complete the internal write leveling process with the host device using the cycle adjust.

公开(公告)号：US11144241B2

公开(公告)日：2021-10-12

申请号：US16534846

申请日：2019-08-07

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen

IPC: G06F3/06 ,  G11C11/40 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4076

Abstract: A host device and memory device function together to perform internal write leveling of a data strobe with a write command within the memory device. The memory device includes a command interface configured to receive write commands from the host device. The memory device also includes an input-output interface configured to receive the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal based at least in part on the write commands. The launch of the internal write signal is based at least in part on an indication from the host device that indicates when to launch the internal write signal relative to a cas write latency (CWL) for the memory device.

公开(公告)号：US10825494B2

公开(公告)日：2020-11-03

申请号：US16683018

申请日：2019-11-13

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen ,  David R. Brown

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C8/18 ,  G11C8/10 ,  G11C11/4096 ,  H04L25/03 ,  G06F13/18 ,  G11C11/4074

Abstract: Methods and devices include an input buffer configured to receive data. Decision feedback equalizer (DFE) circuitry includes a DFE configured to interpret levels of the data from the input buffer and a DFE buffer that stores previous values to control the DFE based on the previous values. Moreover, the DFE circuitry also includes reset circuitry configured to reset the DFE buffer to an initial state. Furthermore, the DFE circuitry includes suppression circuitry configured to suppress resets using the reset circuitry for an interval between write operations to the memory device.

公开(公告)号：US10679683B1

公开(公告)日：2020-06-09

申请号：US16825096

申请日：2020-03-20

Applicant: Micron Technology, Inc.

Inventor： Liang Chen ,  Ming-Bo Liu

IPC: G11C7/04 ,  G11C7/22 ,  G06F13/18 ,  H04L25/03 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/4074 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4093 ,  G11C11/4076

Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device. A walk back circuit is provided to mimic propagation delays of an internal command signal, such as a write command signal, and to speed up the delayed internal command signal an amount equivalent to the propagation delays. The walk back circuit includes a mixture of delay elements provided to mimic propagation delays caused by both gate delays and routing delays.

公开(公告)号：US10452319B1

公开(公告)日：2019-10-22

申请号：US16019116

申请日：2018-06-26

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen

IPC: G06F3/06 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4076

Abstract: A host device and memory device function together to perform internal write leveling of a data strobe with a write command within the memory device. The memory device includes a command interface configured to receive write commands from the host device. The memory device also includes an input-output interface configured to receive the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal based at least in part on the write commands. The launch of the internal write signal is based at least in part on an indication from the host device that indicates when to launch the internal write signal relative to a cas write latency (CWL) for the memory device.