公开(公告)号：US20240290376A1

公开(公告)日：2024-08-29

申请号：US18506202

申请日：2023-11-10

Applicant: Micron Technology, Inc.

Inventor： Wenlun Zhang ,  Hiroki Fujisawa ,  Shinichi Miyatake ,  Yuan He

IPC: G11C11/4091 ,  G11C5/14 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C5/147 ,  G11C11/4096

Abstract: Sense amplifiers for memory devices may include threshold voltage compensation circuitry configured to compensate a threshold voltage offset of a portion of the sense amplifier. Additionally, the sense amplifiers also perform pre-sensing of the portion of the sense amplifier. Moreover, the sense amplifier is configured to perform main sensing and latching in a phase after pre-sensing the portion of the sense amplifier.

公开(公告)号：US11942142B2

公开(公告)日：2024-03-26

申请号：US17931457

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Shinichi Miyatake

IPC: G11C8/08 ,  G11C8/14 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/4085 ,  G11C8/08 ,  G11C8/14 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/4094

Abstract: Memory subword driver circuits with common transistors are disclosed. In some examples, a subword driver block of a memory device includes a plurality of subword drivers each having an output configured to be coupled to a word line coupled to a plurality of memory cells. The outputs of a first subword driver and a second subword driver of the plurality of subword drivers are coupled to a common transistor and a common word driver line, where the first subword driver and the second subword driver are respectively coupled to a first main word line and a second main word line. In such configuration, the first and second subword drivers are coupled in cascade connection so that, responsive to an active first main word line and an inactive common word driver line, a non-active potential is provided to the first subword driver from the second subword driver via the common transistor.

公开(公告)号：US11488655B2

公开(公告)日：2022-11-01

申请号：US17006722

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： Shinichi Miyatake

IPC: G11C8/08 ,  G11C11/408 ,  G11C8/14 ,  G11C11/4074 ,  G11C11/4094

Abstract: Memory subword driver circuits with common transistors are disclosed. In some examples, a subword driver block of a memory device includes a plurality of subword drivers each having an output configured to be coupled to a word line coupled to a plurality of memory cells. The outputs of a first subword driver and a second subword driver of the plurality of subword drivers are coupled to a common transistor and a common word driver line, where the first subword driver and the second subword driver are respectively coupled to a first main word line and a second main word line. In such configuration, the first and second subword drivers are coupled in cascade connection so that, responsive to an active first main word line and an inactive common word driver line, a non-active potential is provided to the first subword driver from the second subword driver via the common transistor.

公开(公告)号：US11176977B2

公开(公告)日：2021-11-16

申请号：US17183604

申请日：2021-02-24

Applicant: Micron Technology, Inc.

Inventor： Toshiyuki Sato ,  Shinichi Miyatake ,  Satoshi Yamanaka

IPC: G11C8/08 ,  G11C29/02 ,  G11C11/408 ,  G11C29/12

Abstract: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.

公开(公告)号：US10276253B2

公开(公告)日：2019-04-30

申请号：US15669256

申请日：2017-08-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shinichi Miyatake

IPC: G11C17/16 ,  G11C17/18 ,  G11C11/4074 ,  H01L23/525 ,  G11C29/00

Abstract: Apparatuses and methods including anti-fuses and for reading and programming same are disclosed herein. An example apparatus may include an anti-fuse element comprising first, second, and third transistors coupled in series between first and second nodes such that the second transistor is between the first and third transistors. The second transistor is configured to be operated such that a punch-through current flows through the second transistor to indicate that the anti-fuse element has been programmed.

公开(公告)号：US09330794B1

公开(公告)日：2016-05-03

申请号：US14638831

申请日：2015-03-04

Applicant: Micron Technology, Inc.

Inventor： Shinichi Miyatake

IPC: G11C17/00 ,  G11C29/00 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C29/783 ,  G11C11/40 ,  G11C17/16 ,  G11C17/18

Abstract: Apparatuses and methods for programming and reading from anti-fuse cells are disclosed herein. For example, a semiconductor device may include a plurality of word lines, a plurality of bit lines, a cell plate, a plurality of cells, and a control circuit. Each of the plurality of cells includes a switch and a capacitor coupled in series between an associated one of the plurality of bit lines and the cell plate, and the switch is controlled by an associated one of the plurality of word lines. The control circuit is configured to provide the cell plate with a first voltage and further configured to change the cell plate from the first voltage to a second voltage before one of the plurality of word lines is activated.

Abstract translation: 本文公开了用于从反熔丝单元编程和读取的装置和方法。 例如，半导体器件可以包括多个字线，多个位线，单元板，多个单元和控制电路。 多个单元中的每一个包括串联耦合在多个位线中的相关联的位线和单元板之间的开关和电容器，并且开关由多个字线中的相关联的一个字线控制。 控制电路被配置为向单元板提供第一电压，并且还被配置为在多个字线中的一个被激活之前将单元板从第一电压改变为第二电压。

公开(公告)号：US20230005519A1

公开(公告)日：2023-01-05

申请号：US17931457

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Shinichi Miyatake

IPC: G11C11/408 ,  G11C8/14 ,  G11C11/4074 ,  G11C11/4094 ,  G11C8/08

Abstract: Memory subword driver circuits with common transistors are disclosed. In some examples, a subword driver block of a memory device includes a plurality of subword drivers each having an output configured to be coupled to a word line coupled to a plurality of memory cells. The outputs of a first subword driver and a second subword driver of the plurality of subword drivers are coupled to a common transistor and a common word driver line, where the first subword driver and the second subword driver are respectively coupled to a first main word line and a second main word line. In such configuration, the first and second subword drivers are coupled in cascade connection so that, responsive to an active first main word line and an inactive common word driver line, a non-active potential is provided to the first subword driver from the second subword driver via the common transistor.

公开(公告)号：US10937476B2

公开(公告)日：2021-03-02

申请号：US16450696

申请日：2019-06-24

Applicant: Micron Technology, Inc.

Inventor： Toshiyuki Sato ,  Shinichi Miyatake ,  Satoshi Yamanaka

IPC: G11C8/08 ,  G11C29/02 ,  G11C11/408 ,  G11C29/12

Abstract: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.

公开(公告)号：US10854272B1

公开(公告)日：2020-12-01

申请号：US16450723

申请日：2019-06-24

Applicant: Micron Technology, Inc.

Inventor： Toshiyuki Sato ,  Shinichi Miyatake

IPC: G11C8/00 ,  G11C11/408 ,  G11C11/4076

Abstract: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.

公开(公告)号：US10714158B2

公开(公告)日：2020-07-14

申请号：US16269886

申请日：2019-02-07

Applicant: Micron Technology, Inc.

Inventor： Shinichi Miyatake

IPC: G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/10

Abstract: Apparatus and methods are disclosed, including an apparatus having a first transistor configured to be coupled to a first bit line, and a control circuit configured to supply a gate of the first transistor with a first voltage to turn on the first transistor, and to supply the gate of the first transistor with a second voltage higher than the first voltage to strengthen a current drive capability of the first transistor.