公开(公告)号：US20140254297A1

公开(公告)日：2014-09-11

申请号：US14036997

申请日：2013-09-25

Applicant: Macronix International Co., Ltd.

Inventor： Shuo-Nan Hung ,  Chi Lo ,  Chun-Hsiung Hung

IPC: G11C29/04

CPC classification number: G11C29/70 ,  G11C29/04 ,  G11C29/72 ,  G11C29/808 ,  G11C29/82

Abstract: An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns.

Abstract translation: 集成电路包括排列成在阵列中执行维修的行，主列和冗余列的存储器单元阵列。 主列和冗余列分为行块。 位线将主列连接到指示冗余列修复状态的状态存储器。 集成电路接收命令，并且利用该命令访问的存储器的一部分中的特定行的特定块的修复状态对状态存储器进行更新。 或者或组合地，状态存储器的尺寸不足以存储主列的多个行块的修复状态。

公开(公告)号：US20130235674A1

公开(公告)日：2013-09-12

申请号：US13871891

申请日：2013-04-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Chi Lo

IPC: G11C16/28 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C11/56 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/28 ,  Y10T29/49117

Abstract: Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement.

Abstract translation: 各种实施例解决了诸如3D垂直门闪存和多电平单元存储器的各种存储器架构中的源侧感测困难的各种困难。 一个这样的困难是，通过源侧感测，信号幅度显着小于漏极侧感测。 另一个这样的困难是与多电平单元存储器相关联的噪声和降低的感测裕度。 在一些实施例中，位线在施加读取偏置布置之前被选择性地放电。