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公开(公告)号：US10290364B2
公开(公告)日：2019-05-14
申请号：US14849412
申请日：2015-09-09
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Shuo-Nan Hung , Chi Lo , Chun-Hsiung Hung
Abstract: An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns.
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公开(公告)号：US20140258811A1
公开(公告)日：2014-09-11
申请号：US13951130
申请日：2013-07-25
Applicant: Macronix International Co., Ltd.
Inventor： Yi-Ching Liu , Chi Lo , Shuo-Nan Hung , Chun-Hsiung Hung
CPC classification number: G06F11/1044 , G06F11/1008 , G06F11/1068 , G11B20/1833 , G11C7/1006
Abstract: A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, and a multi-level buffer structure between the memory array and an input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first buffer having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations.
Abstract translation: 一种设备包括存储与数据相对应的数据和纠错码ECC的存储器阵列，以及存储器阵列和输入/输出数据路径之间的多级缓冲器结构。 存储器阵列包括用于页模式操作的多条数据线。 缓冲器结构包括：第一缓冲器，其具有连接到用于数据页的多条数据线中的相应数据线的存储单元;耦合到第一缓冲器中用于存储至少一页数据的存储单元的第二缓冲器;以及 耦合到第二缓冲器和输入/输出数据路径的第三缓冲器。 该设备包括耦合到多级缓冲器的逻辑，用于在存储器阵列和通过多级缓冲器的输入/输出路径之间的移动期间在页面读取和页面写入操作中的至少一个上执行数据页面上的逻辑处理。
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公开(公告)号：US09478314B2
公开(公告)日：2016-10-25
申请号：US14486963
申请日：2014-09-15
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Hungwei Lu , Wei-An Lai , Shuo-Nan Hung , Chi Lo
CPC classification number: G11C29/42 , G11C16/00 , G11C29/44 , G11C29/52 , G11C2029/0411
Abstract: An integrated circuit memory includes a memory array, including a plurality of data lines. A buffer structure is coupled to the plurality of data lines, including a plurality of storage elements to store bit-level status values for the plurality of data lines. The memory includes logic to indicate bundle-level status values of corresponding bundles of storage elements in the buffer structure based on the bit-level status values of bits in the corresponding bundles. A plurality of bundle status circuits is arranged in a daisy chain and coupled to respective bundles in the buffer structure, producing an output of the daisy chain indicating detection of a bundle in the first status. Control circuitry executes cycles to determine the output of the daisy chain, each cycle clearing a bundle status circuit indicating the first status if the output indicates detection of a bundle in the first status in the cycle.
Abstract translation: 集成电路存储器包括包括多条数据线的存储器阵列。 缓冲结构耦合到多条数据线，包括多个存储元件以存储多条数据线的位级状态值。 存储器包括基于相应束中的位的位级状态值来指示缓冲器结构中的对应的存储元件束的束级状态值的逻辑。 多个束状态电路被布置在菊花链中并且耦合到缓冲器结构中的各个束，从而产生指示在第一状态下检测束的菊花链的输出。 控制电路执行周期以确定菊花链的输出，每个周期清除捆绑状态电路，指示第一状态，如果输出指示在周期中处于第一状态的捆绑检测。
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公开(公告)号：US09147485B2
公开(公告)日：2015-09-29
申请号：US13871891
申请日：2013-04-26
Applicant: Macronix International Co., Ltd.
Inventor： Chun-Hsiung Hung , Chi Lo
CPC classification number: G11C16/26 , G11C11/56 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/28 , Y10T29/49117
Abstract: Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement.
Abstract translation: 各种实施例解决了诸如3D垂直门闪存和多电平单元存储器的各种存储器架构中的源侧感测困难的各种困难。 一个这样的困难是，通过源侧感测，信号幅度显着小于漏极侧感测。 另一个这样的困难是与多电平单元存储器相关联的噪声和降低的感测裕度。 在一些实施例中，位线在施加读取偏置布置之前被选择性地放电。
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公开(公告)号：US09773571B2
公开(公告)日：2017-09-26
申请号：US14572166
申请日：2014-12-16
Applicant: Macronix International Co., Ltd.
Inventor： Chi Lo , Shuo-Nan Hung , Chun-Hsiung Hung
CPC classification number: G11C29/78 , G06F2201/85 , G11C29/76
Abstract: An integrated circuit including a memory, an array cache, and a cache replacement store is described. The memory includes a primary array and a redundant array. The integrated circuit also includes circuitry configured to transfer data into or out of the primary array using the array cache. For defective locations in the array cache, the circuitry is configured to use the cache replacement store in the transfer of data in place of the defective locations in the array cache, and map addresses in the primary array corresponding to the defective locations in the cache array to the redundant array.
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Patent Agency Ranking
公开(公告)号：US20160170853A1
公开(公告)日：2016-06-16
申请号：US14572166
申请日：2014-12-16
Applicant: Macronix International Co., Ltd.
Inventor： Chi Lo , Shuo-Nan Hung , Chun-Hsiung Hung
CPC classification number: G11C29/78 , G06F2201/85 , G11C29/76
Abstract: An integrated circuit including a memory, an array cache, and a cache replacement store is described. The memory includes a primary array and a redundant array. The integrated circuit also includes circuitry configured to transfer data into or out of the primary array using the array cache. For defective locations in the array cache, the circuitry is configured to use the cache replacement store in the transfer of data in place of the defective locations in the array cache, and map addresses in the primary array corresponding to the defective locations in the cache array to the redundant array.
Abstract translation: 描述了包括存储器，阵列高速缓存和高速缓存替换存储器的集成电路。 内存包括主阵列和冗余阵列。 集成电路还包括被配置为使用数组高速缓存将数据传入或传出主阵列的电路。 对于阵列高速缓存中的不良位置，电路被配置为在代替数据高速缓存中的有缺陷的位置的数据传输中使用高速缓存替换存储器，并且对应于高速缓存阵列中的缺陷位置的映射地址 到冗余阵列。
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7.发明授权Memory integrated circuit with a page register/status memory capable of storing only a subset of row blocks of main column blocks 有权具有能够仅存储主列块的行块的子集的页寄存器/状态存储器的存储器集成电路公开(公告)号：US09165680B2
公开(公告)日：2015-10-20
申请号：US14036997
申请日：2013-09-25
Applicant: Macronix International Co., Ltd.
Inventor： Shuo-Nan Hung , Chi Lo , Chun-Hsiung Hung
CPC classification number: G11C29/70 , G11C29/04 , G11C29/72 , G11C29/808 , G11C29/82
Abstract: An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns.
Abstract translation: 集成电路包括排列成在阵列中执行维修的行，主列和冗余列的存储器单元阵列。 主列和冗余列分为行块。 位线将主列连接到指示冗余列修复状态的状态存储器。 集成电路接收命令，并且利用该命令访问的存储器的一部分中的特定行的特定块的修复状态对状态存储器执行更新。 或者或组合地，状态存储器的尺寸不足以存储主列的多个行块的修复状态。
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公开(公告)号：US11189339B1
公开(公告)日：2021-11-30
申请号：US16886995
申请日：2020-05-29
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yi-Ching Liu , Chi Lo
IPC: G11C16/10 , G11C11/4096 , G11C11/4091 , G11C11/4094 , G05F3/26 , G11C11/4074 , H03M1/46 , G06F9/38 , G11C11/408 , G11C13/00 , G11C16/04
Abstract: A memory device includes: a memory array including a plurality of memory cells and a plurality of bit lines; and a current converting circuit, coupled to the memory array. In executing a calculation operation, the memory cells of the memory array generate a source current corresponding to a calculation operation result. The source current is converted by the current converting circuit into an output value for being an input signal provided to a next calculation operation.
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公开(公告)号：US09690650B2
公开(公告)日：2017-06-27
申请号：US13951130
申请日：2013-07-25
Applicant: Macronix International Co., Ltd.
Inventor： Yi-Ching Liu , Chi Lo , Shuo-Nan Hung , Chun-Hsiung Hung
CPC classification number: G06F11/1044 , G06F11/1008 , G06F11/1068 , G11B20/1833 , G11C7/1006
Abstract: A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, and a multi-level buffer structure between the memory array and an input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first buffer having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations.
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公开(公告)号：US09570186B2
公开(公告)日：2017-02-14
申请号：US14853583
申请日：2015-09-14
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chun-Hsiung Hung , Chi Lo
CPC classification number: G11C16/26 , G11C11/56 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/28 , Y10T29/49117
Abstract: Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement.
Abstract translation: 各种实施例解决了诸如3D垂直门闪存和多电平单元存储器的各种存储器架构中的源侧感测困难的各种困难。 一个这样的困难是，通过源侧感测，信号幅度显着小于漏极侧感测。 另一个这样的困难是与多电平单元存储器相关联的噪声和降低的感测裕度。 在一些实施例中，位线在施加读取偏置布置之前被选择性地放电。
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