公开(公告)号：US5946591A

公开(公告)日：1999-08-31

申请号：US553219

申请日：1995-11-07

申请人： Shigeo Ashigaki ,  Kazuhiro Hamamoto

发明人： Shigeo Ashigaki ,  Kazuhiro Hamamoto

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L21/4763

CPC分类号： H01L27/10852 ,  H01L21/31056 ,  H01L21/76819 ,  H01L27/105 ,  H01L27/10808

摘要： A manufacturing method for semiconductor devices such as dynamic RAM, etc. which removes the layer part more on the high position than an arbitrary position on a step forming a gradation by just a prescribed thickness when flattening a layer with a gradation formed of a high position part and a low position part. Then the projecting part created after the etching existing more on the low position side than at the arbitrary position of the gradation is eliminated by heat treatment.

摘要翻译： 一种用于诸如动态RAM等的半导体器件的制造方法，其中，当将由高位置形成的层次进行平坦化时，在高位置上除去比在形成灰度的台阶上的任意位置更多的层部分 部分和低位部分。 然后，通过热处理消除了在比灰度的任意位置更多地存在于低位置侧的蚀刻之后产生的突出部分。

公开(公告)号：US5872060A

公开(公告)日：1999-02-16

申请号：US738621

申请日：1996-10-29

申请人： Shigeo Ashigaki ,  Kazuhiro Hamamoto

发明人： Shigeo Ashigaki ,  Kazuhiro Hamamoto

IPC分类号： H01L21/3105 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/302

CPC分类号： H01L27/10844 ,  H01L21/31053 ,  H01L27/1052

摘要： A semiconductor manufacturing method for devices, such as a DRAM, having a plurality of circuit elements of at least two substantially different heights (such as memory-cells vs. peripheral circuits) on a common semiconductor substrate. A plurality of circuit elements of at least two substantially different heights are formed on a common semiconductor substrate. A common insulating layer, such as BPSG, whose top surface has substantial variation in height above the substrate, is deposited over the circuit elements. A resist mask layer is deposited over the insulating layer with openings over high portions of the insulating layer's top surface exceeding a first predetermined height. Then the insulating layer's high portions are etched down to a second predetermined height to make its overall top surface more even, and the resist mask layer removed. The enables a working layer that would be easily damaged by substantial height variation to be deposited on the evened insulating layer.

摘要翻译： 在公共半导体衬底上具有多个具有至少两个基本上不同的高度的电路元件（诸如存储单元与外围电路）的器件的半导体制造方法。 在共同的半导体衬底上形成有至少两个基本上不同的高度的多个电路元件。 诸如BPSG的公共绝缘层，其顶表面在衬底上方的高度具有显着变化，沉积在电路元件上。 抗蚀剂掩模层沉积在绝缘层上方，绝缘层顶表面的高部分上的开口超过第一预定高度。 然后将绝缘层的高部分蚀刻到第二预定高度，使其整个顶表面更均匀，并且去除抗蚀剂掩模层。 这使得能够容易地被大量的高度变化损坏的工作层沉积在均匀的绝缘层上。