公开(公告)号：US11619719B2

公开(公告)日：2023-04-04

申请号：US16265364

申请日：2019-02-01

Applicant: Marc Loinaz

Inventor： Marc Loinaz

IPC: G01S7/4865 ,  G01S7/481 ,  G01S7/4863 ,  G01S17/88 ,  H03K5/135 ,  H04J3/06 ,  H03K5/133 ,  H04L7/00

Abstract: A sensor network, which includes a sensor controller serially coupled to a plurality of sensor modules, is configured to program the sensor modules so as to transfer measurement data to the sensor controller and to synchronize the sensor modules to picosecond accuracy via on-chip or on-module custom circuits and a physical layer protocol. The sensor network has applications for use in PET, LiDAR or FLIM applications. Synchronization, within picosecond accuracy, is achieved through use of a picosecond time digitization circuit. Specifically, the picosecond time digitization circuit is used to measure on-chip delays with high accuracy and precision. The delay measurements are directly comparable between separate chips even with voltage and temperature variations between chips.

公开(公告)号：US20190268003A1

公开(公告)日：2019-08-29

申请号：US16265400

申请日：2019-02-01

Applicant: Marc Loinaz

Inventor： Marc Loinaz

IPC: H03L7/06 ,  G01N15/14 ,  G01S17/10 ,  G01S7/486 ,  G01T1/29

Abstract: A sensor network, which includes a sensor controller serially coupled to a plurality of sensor modules, is configured to program the sensor modules so as to transfer measurement data to the sensor controller and to synchronize the sensor modules to picosecond accuracy via on-chip or on-module custom circuits and a physical layer protocol. The sensor network has applications for use in PET, LiDAR or FLIM applications. Synchronization, within picosecond accuracy, is achieved through use of a picosecond time digitization circuit. Specifically, the picosecond time digitization circuit is used to measure on-chip delays with high accuracy and precision. The delay measurements are directly comparable between separate chips even with voltage and temperature variations between chips.

公开(公告)号：US08433018B2

公开(公告)日：2013-04-30

申请号：US12130732

申请日：2008-05-30

Applicant: Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Sekhar Narayanaswami ,  Nikhil Acharya ,  Dean Liu

Inventor： Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Sekhar Narayanaswami ,  Nikhil Acharya ,  Dean Liu

IPC: H04L7/00

CPC classification number: H03L7/0893 ,  H03K5/133 ,  H03K2005/00052 ,  H03L7/081 ,  H03L7/0895 ,  H03L7/093 ,  H03L7/0998 ,  H03L7/18

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract translation: 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。

公开(公告)号：US20110231692A1

公开(公告)日：2011-09-22

申请号：US12728101

申请日：2010-03-19

Applicant: Marc Loinaz

Inventor： Marc Loinaz

IPC: G06F1/04 ,  G06F12/00

CPC classification number: G06F12/0246 ,  G06F1/08

Abstract: Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input data and sending output data signals along a series of signal lines with a signal strength, and a signal modulator configured to determine the signal strength based on a control input. Some embodiments include a clock generation circuit for receiving clock reference and sending output clock signals along a series of signal lines with a signal character, and a signal modulator configured to determine the signal character based on a control input.

Abstract translation: 本发明的实施例涉及可编程数据寄存器电路和可编程时钟生成电路。例如，一些实施例包括用于接收输入数据并沿着具有信号强度的一系列信号线发送输出数据信号的缓冲电路，以及配置为 根据控制输入确定信号强度。 一些实施例包括用于接收时钟参考并且沿着一系列具有信号字符的信号线发送输出时钟信号的时钟产生电路，以及被配置为基于控制输入来确定信号字符的信号调制器。

公开(公告)号：US07432750B1

公开(公告)日：2008-10-07

申请号：US11296786

申请日：2005-12-07

Applicant: Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Shekhar Narayanaswami ,  Nikhil Acharya ,  Dean Liu

Inventor： Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Shekhar Narayanaswami ,  Nikhil Acharya ,  Dean Liu

IPC: H03B21/00 ,  H03L7/06

CPC classification number: H03L7/0893 ,  H03K5/133 ,  H03K2005/00052 ,  H03L7/081 ,  H03L7/0895 ,  H03L7/093 ,  H03L7/0998 ,  H03L7/18

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract translation: 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。

公开(公告)号：US20230006677A1

公开(公告)日：2023-01-05

申请号：US17942077

申请日：2022-09-09

Applicant: Marc Loinaz

Inventor： Marc Loinaz

IPC: H03L7/06 ,  G01N15/14 ,  G01S7/4865 ,  G01T1/29 ,  G01S17/26 ,  G01S17/88

Abstract: A sensor network, which includes a sensor controller serially coupled to a plurality of sensor modules, is configured to program the sensor modules so as to transfer measurement data to the sensor controller and to synchronize the sensor modules to picosecond accuracy via on-chip or on-module custom circuits and a physical layer protocol. The sensor network has applications for use in PET, LiDAR or FLIM applications. Synchronization, within picosecond accuracy, is achieved through use of a picosecond time digitization circuit. Specifically, the picosecond time digitization circuit is used to measure on-chip delays with high accuracy and precision. The delay measurements are directly comparable between separate chips even with voltage and temperature variations between chips.

公开(公告)号：US20210152269A1

公开(公告)日：2021-05-20

申请号：US17138844

申请日：2020-12-30

Applicant: Marc Loinaz

Inventor： Marc Loinaz

IPC: H04J3/06 ,  H03K5/135 ,  H04L7/00 ,  H03K5/133

Abstract: A sensor network, which includes a sensor controller serially coupled to a plurality of sensor modules, is configured to program the sensor modules so as to transfer measurement data to the sensor controller and to synchronize the sensor modules to picosecond accuracy via on-chip or on-module custom circuits and a physical layer protocol. The sensor network has applications for use in PET, LiDAR or FLIM applications. Synchronization, within picosecond accuracy, is achieved through use of a picosecond time digitization circuit. Specifically, the picosecond time digitization circuit is used to measure on-chip delays with high accuracy and precision. The delay measurements are directly comparable between separate chips even with voltage and temperature variations between chips.

公开(公告)号：US07919957B2

公开(公告)日：2011-04-05

申请号：US12723538

申请日：2010-03-12

Applicant: Shwetabh Verma ,  Marc Loinaz

Inventor： Shwetabh Verma ,  Marc Loinaz

IPC: G05F1/40

CPC classification number: G05F1/575

Abstract: A digital linear voltage regulator includes a comparator, a finite state machine, and a current digital-to-analog converter (DAC). The comparator is preferably coupled to receive a reference voltage and an operating voltage supplied to a dynamic load. The comparator generates, during a clock cycle, a binary output based on a comparison between reference and operating voltages. The finite state machine (FSM) is coupled to receive at least one control signal that indicates a target operating state for the digital linear voltage regulator. The FSM receives the binary output from the comparator and generates a digital word, during a clock cycle, based on the target operating state of the digital linear voltage regulator and on the binary output. The current DAC is coupled to the FSM, receives the digital word and delivers current at the desired voltage to the dynamic load.

Abstract translation: 数字线性稳压器包括比较器，有限状态机和当前的数模转换器（DAC）。 优选地，比较器被耦合以接收提供给动态负载的参考电压和工作电压。 比较器根据参考电压和工作电压之间的比较，在时钟周期内产生二进制输出。 有限状态机（FSM）被耦合以接收指示数字线性电压调节器的目标操作状态的至少一个控制信号。 FSM从比较器接收二进制输出，并在时钟周期内根据数字线性稳压器的目标工作状态和二进制输出产生数字字。 当前的DAC耦合到FSM，接收数字字，并将电流以期望的电压传递给动态负载。

公开(公告)号：US20080048734A1

公开(公告)日：2008-02-28

申请号：US11861690

申请日：2007-09-26

Applicant: Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Narayanaswami ,  Nikhil Acharya ,  Dean Liu

Inventor： Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Narayanaswami ,  Nikhil Acharya ,  Dean Liu

IPC: H03B21/00

CPC classification number: H03L7/0893 ,  H03K5/133 ,  H03K2005/00052 ,  H03L7/081 ,  H03L7/0895 ,  H03L7/093 ,  H03L7/0998 ,  H03L7/18

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract translation: 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。

公开(公告)号：US07323916B1

公开(公告)日：2008-01-29

申请号：US11321412

申请日：2005-12-29

Applicant: Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Shekhar Narayanaswami ,  Nikhil Acharya ,  Dean Liu

Inventor： Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Shekhar Narayanaswami ,  Nikhil Acharya ,  Dean Liu

IPC: H03L7/06

CPC classification number: H03L7/0893 ,  H03K5/133 ,  H03K2005/00052 ,  H03L7/081 ,  H03L7/0895 ,  H03L7/093 ,  H03L7/0998 ,  H03L7/18

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract translation: 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。