公开(公告)号：US20070198778A1

公开(公告)日：2007-08-23

申请号：US11592835

申请日：2006-11-03

Applicant: Shailender Chaudhry ,  Marc Tremblay

Inventor： Shailender Chaudhry ,  Marc Tremblay

IPC: G06F12/00

CPC classification number: G06F12/0897

Abstract: One embodiment of the present invention provides a system that enforces memory-reference ordering requirements at an L2 cache. During operation, the system receives a load at the L2 cache, wherein the load previously caused a miss at an L1 cache. Upon receiving the load, the system performs a lookup for the load in reflections of store buffers associated with other L1 caches. These reflections are located at the L2 cache, and each reflection contains addresses for stores in a corresponding store buffer associated with an L1 cache, and possibly contains data that was overwritten by the stores. If the lookup generates a hit, which indicates that the load may potentially interfere with a store, the system causes the load to wait to execute until the store commits.

Abstract translation: 本发明的一个实施例提供一种在L2高速缓存上实施存储器参考排序要求的系统。 在操作期间，系统在L2高速缓存中接收负载，其中负载先前在L1高速缓存引起了错过。 在接收到负载后，系统以与其他L1高速缓存相关联的存储缓冲器的反射来执行对负载的查找。 这些反射位于L2高速缓存中，每个反射都包含与L1缓存相关联的存储缓冲器中的存储地址，并且可能包含由存储器覆盖的数据。 如果查找生成一个命中，这表明该负载可能潜在地干扰一个存储，系统会导致负载等待执行，直到存储提交。

公开(公告)号：US20070186081A1

公开(公告)日：2007-08-09

申请号：US11367814

申请日：2006-03-03

Applicant: Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

Inventor： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

IPC: G06F9/30

CPC classification number: G06F9/3863 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857

Abstract: One embodiment of the present invention provides a system which supports out-of-order issue in a processor that normally executes instructions in-order. The system starts by issuing instructions from an issue queue in program order during a normal-execution mode. While issuing the instructions, the system determines if any instruction in the issue queue has an unresolved short-latency data dependency which depends on a short-latency operation. If so, the system generates a checkpoint and enters an out-of-order-issue mode, wherein instructions in the issue queue with unresolved short-latency data dependencies are held and not issued, and wherein other instructions in the issue queue without unresolved data dependencies are allowed to issue out-of-order.

Abstract translation: 本发明的一个实施例提供了一种支持处理器中的乱序问题的系统，其通常按顺序执行指令。 在正常执行模式期间，系统以程序顺序从发出队列发出指令开始。 在发出指令时，系统确定发出队列中的任何指令是否具有取决于短暂延迟操作的未解决的短延迟数据依赖性。 如果是这样，系统将生成一个检查点并进入无序发布模式，其中具有未解决的短延迟数据依赖性的发布队列中的指令被保留并且不发出，并且其中发出队列中的其他指令没有未解析的数据 依赖关系被允许发布无序。

公开(公告)号：US20070006195A1

公开(公告)日：2007-01-04

申请号：US11082281

申请日：2005-03-16

Applicant: Christof Braun ,  Quinn Jacobson ,  Shailender Chaudhry ,  Marc Tremblay

Inventor： Christof Braun ,  Quinn Jacobson ,  Shailender Chaudhry ,  Marc Tremblay

IPC: G06F9/45

CPC classification number: G06F9/383 ,  G06F9/3838 ,  G06F9/3863

Abstract: Explicit software control is used for data speculations. The explicit software control is applied at selected locations in a computer program to provide the benefit of data speculation while eliminating the need for hardware to perform data speculation. A computer-based method first determines, via explicit software control, whether data speculation for an item, a variable, a pointer, an address, etc., is needed. Upon determining that data speculation for the item is needed, the data speculation is performed under explicit software control. Conversely, if the explicit software control determines that data speculation is not needed, e.g., the value of the item typically obtained by execution of a long latency instruction, is available, an original code segment is executed using an actual value of the item.

Abstract translation: 显式软件控制用于数据推测。 显式软件控制应用于计算机程序中的选定位置，以提供数据推测的优点，同时不需要硬件来执行数据推测。 基于计算机的方法首先通过显式软件控制来确定是否需要对项目，变量，指针，地址等的数据推测。 在确定需要该项目的数据推测时，数据推测是在明确的软件控制下执行的。 相反，如果显式软件控制确定不需要数据推测，例如，通常通过执行长延迟指令获得的项目的值是可用的，则使用该项目的实际值来执行原始代码段。

公开(公告)号：US07114060B2

公开(公告)日：2006-09-26

申请号：US10686061

申请日：2003-10-14

Applicant: Shailender Chaudhry ,  Marc Tremblay

Inventor： Shailender Chaudhry ,  Marc Tremblay

IPC: G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865

Abstract: One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order.

Abstract translation: 本发明的一个实施例提供了一种系统，其有助于在按照程序顺序执行时，推迟执行具有未解决的数据依赖性的指令。 在正常执行模式下，系统以程序顺序发出执行指令。 在执行指令期间遇到未解决的数据依赖性时，系统产生一个检查点，随后可以使用该检查点将程序的执行返回到指令点。 接下来，系统以执行模式执行后续指令，其中由于未解决的数据依赖性而不能执行的指令被延迟，并且其中其他非延迟指令以程序顺序执行。

公开(公告)号：US20060101254A1

公开(公告)日：2006-05-11

申请号：US11296599

申请日：2005-12-06

Applicant: Marc Tremblay ,  Shailender Chaudhry ,  Quinn Jacobson

Inventor： Marc Tremblay ,  Shailender Chaudhry ,  Quinn Jacobson

IPC: G06F9/44

CPC classification number: G06F9/528 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3857 ,  Y10S707/99953

Abstract: One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the STE instruction. Changes made during this transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.

公开(公告)号：US20050273583A1

公开(公告)日：2005-12-08

申请号：US11083263

申请日：2005-03-16

Applicant: Paul Caprioli ,  Shailender Chaudhry ,  Marc Tremblay

Inventor： Paul Caprioli ,  Shailender Chaudhry ,  Marc Tremblay

IPC: G06F9/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/45 ,  G06F12/08

CPC classification number: G06F9/30087 ,  G06F9/3004 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857

Abstract: One embodiment of the present invention provides a system that facilitates executing a memory barrier (membar) instruction in an execute-ahead processor, wherein the membar instruction forces buffered loads and stores to complete before allowing a following instruction to be issued. During operation in a normal-execution mode, the processor issues instructions for execution in program order. Upon encountering a membar instruction, the processor determines if the load buffer and store buffer contain unresolved loads and stores. If so, the processor defers the membar instruction and executes subsequent program instructions in execute-ahead mode. In execute-ahead mode, instructions that cannot be executed because of an unresolved data dependency are deferred, and other non-deferred instructions are executed in program order. When all stores and loads that precede the membar instruction have been committed to memory from the store buffer and the load buffer, the processor enters a deferred mode and executes the deferred instructions, including the membar instruction, in program order. If all deferred instructions have been executed, the processor returns to the normal-execution mode and resumes execution from the point where the execute-ahead mode left off.

Abstract translation: 本发明的一个实施例提供了一种便于在执行前处理器中执行存储器屏障（membar）指令的系统，其中，在允许执行后续指令之前，该指令强制缓冲的负载和存储完成。 在正常执行模式下的操作期间，处理器以程序顺序发出执行指令。 在遇到一条指令时，处理器确定加载缓冲区和存储缓冲区是否包含未解决的负载和存储。 如果是这样，则处理器延迟膜指令，并以执行模式执行后续的程序指令。 在执行提前模式下，由于未解决的数据依赖关系而无法执行的指令被延迟，并且其他非延迟指令以程序顺序执行。 当存储缓冲区和加载缓冲区之前的所有存储和负载已经提交到存储缓冲区的内存中时，处理器以程序顺序进入延迟模式并执行延迟指令，包括指令指令。 如果所有延迟指令都已执行，则处理器返回到正常执行模式，并从执行方式退出的点恢复执行。

公开(公告)号：US20050223201A1

公开(公告)日：2005-10-06

申请号：US11095644

申请日：2005-03-30

Applicant: Marc Tremblay ,  Shailender Chaudhry ,  Quinn Jacobson

Inventor： Marc Tremblay ,  Shailender Chaudhry ,  Quinn Jacobson

IPC: G06F9/00 ,  G06F9/38

CPC classification number: G06F9/383 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3863

Abstract: One embodiment of the present invention provides a processor that facilitates rapid progress while speculatively executing instructions in scout mode. During normal operation, the processor executes instructions in a normal execution mode. Upon encountering a stall condition, the processor executes the instructions in a scout mode, wherein the instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor. While speculatively executing the instructions in scout mode, the processor maintains dependency information for each register indicating whether or not a value in the register depends on an unresolved data-dependency. If an instruction to be executed in scout mode depends on an unresolved data dependency, the processor executes the instruction as a NOOP so that the instruction executes rapidly without tying up computational resources. The processor also propagates dependency information indicating an unresolved data dependency to a destination register for the instruction.

Abstract translation: 本发明的一个实施例提供了一种在侦察模式下推测性地执行指令时促进快速进展的处理器。 在正常操作期间，处理器以正常执行模式执行指令。 在遇到停顿状态时，处理器以侦察模式执行指令，其中推测性地执行指令以预取将来的负载，但是其中结果未被提交到处理器的架构状态。 当在侦察模式中推测性地执行指令时，处理器维护每个寄存器的依赖性信息，指示寄存器中的值是否取决于未解决的数据依赖性。 如果以侦察模式执行的指令取决于未解决的数据依赖关系，则处理器将该指令执行为NOOP，以使指令快速执行，而不占用计算资源。 处理器还将指示未解决的数据依赖关系的依赖信息传播到指令的目的地寄存器。

公开(公告)号：US20050223194A1

公开(公告)日：2005-10-06

申请号：US11082282

申请日：2005-03-16

Applicant: Marc Tremblay ,  Shailender Chaudhry ,  Quinn Jacobson

Inventor： Marc Tremblay ,  Shailender Chaudhry ,  Quinn Jacobson

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30061 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/3842

Abstract: A user is provided with means to sample memory hierarchy via software. This allows a user to enhance memory-level parallelism via software. A status of information needed for execution of a second computer program instruction is read in response to execution of a first computer program instruction. Execution continues with execution of the second computer program instruction upon the status being a first status. Alternatively, a third computer program instruction is executed upon the status being a second status different from the first status. Thus, execution of the first computer program instruction allows control of the memory hierarchy, which in turn give the user control of the memory hierarchy.

Abstract translation: 为用户提供了通过软件对存储器层次结构进行抽样的方法。 这允许用户通过软件来增强内存级并行性。 响应于第一计算机程序指令的执行，读取执行第二计算机程序指令所需的信息的状态。 在状态为第一状态时，继续执行第二计算机程序指令。 或者，在状态是与第一状态不同的第二状态的情况下执行第三计算机程序指令。 因此，第一计算机程序指令的执行允许对存储器层次的控制，这进而使得用户对存储器层级进行控制。

公开(公告)号：US06721944B2

公开(公告)日：2004-04-13

申请号：US09761226

申请日：2001-01-16

Applicant: Shailender Chaudhry ,  Marc Tremblay

Inventor： Shailender Chaudhry ,  Marc Tremblay

IPC: G06F945

CPC classification number: G06F9/3851 ,  G06F9/3842

Abstract: One embodiment of the present invention provides a system that marks memory elements based upon how information retrieved from the memory elements affects speculative program execution. This system operates by allowing a programmer to examine source code that is to be compiled into executable code for a head thread that executes program instructions, and for a speculative thread that executes program instructions in advance of the head thread. During read operations to memory elements by the speculative thread, this executable code generally causes the speculative thread to update status information associated with the memory elements to indicate that the memory elements have been read by the speculative thread. Next, the system allows the programmer to identify a given read operation directed to a given memory element, wherein a given value retrieved from the given memory element during the given read operation does not affect subsequent execution of the speculative thread. The programmer is then allowed to insert a hint into the source code specifying that the speculative thread is not to update status information during the given read operation directed to the given memory element. Next, the system compiles the source code, including the hint, into the executable code, so that during the given read operation, the executable code does not cause the speculative thread to update status information associated with the given memory element to indicate that the given memory element has been read by the speculative thread.

Abstract translation: 本发明的一个实施例提供了一种基于如何从存储器元件检索的信息影响推测程序执行来标记存储器元件的系统。 该系统通过允许程序员检查要编译成用于执行程序指令的头部线程的可执行代码的源代码，以及在头部线程之前执行程序指令的推测线程。 在通过推测线程对存储器元件的读取操作期间，该可执行代码通常导致推测线程更新与存储器元件相关联的状态信息，以指示存储器元件已被推测性线程读取。 接下来，系统允许程序员识别针对给定存储器元件的给定读取操作，其中在给定读取操作期间从给定存储器元件检索的给定值不影响推测线程的后续执行。 然后，程序员可以在源代码中插入提示，指定在给定的给定内存元素的给定读操作期间，推测线程不更新状态信息。 接下来，系统将源代码（包括提示）编译到可执行代码中，使得在给定的读取操作期间，可执行代码不会导致推测线程更新与给定存储器元件相关联的状态信息，以指示给定的 内存元素已被推测线程读取。

公开(公告)号：US06704862B1

公开(公告)日：2004-03-09

申请号：US09591142

申请日：2000-06-09

Applicant: Shailender Chaudhry ,  Marc Tremblay

Inventor： Shailender Chaudhry ,  Marc Tremblay

IPC: G06F938

CPC classification number: G06F9/3842 ,  G06F9/3861

Abstract: One embodiment of the present invention provides a system that supports exception handling through use of a conditional trap instruction. The system supports a head thread that executes program instructions and a speculative thread that speculatively executes program instructions in advance of the head thread. During operation, the system uses the speculative thread to execute code, which includes an instruction that can cause an exception condition. After the instruction is executed, the system determines if the instruction caused the exception condition. If so, the system writes an exception condition indicator to a register. At some time in the future, the system executes a conditional trap instruction which examines a value in the register. If the value in the register is an exception condition indicator, the system executes a trap handling routine to handle the exception condition. Otherwise, the system proceeds with execution of the code. In one embodiment of the present invention, prior to executing the instruction, the system allows a compiler to optimize a program containing the instruction. This optimization process includes scheduling an exception testing instruction associated with the instruction to occupy a free instruction slot following the instruction. This exception testing instruction determines if the instruction causes the exception condition. In one embodiment of the present invention, the trap handling routine triggers a rollback operation to undo operations performed by the speculative thread.

Abstract translation: 本发明的一个实施例提供一种通过使用条件陷阱指令来支持异常处理的系统。 该系统支持执行程序指令的头线程和在头部线程之前推测性地执行程序指令的推测线程。 在运行期间，系统使用推测线程来执行代码，其中包含可能导致异常情况的指令。 执行指令后，系统确定指令是否引起异常情况。 如果是这样，系统会将一个异常状态指示器写入寄存器。 在将来的某个时间，系统执行条件陷阱指令，检查寄存器中的值。 如果寄存器中的值是异常条件指示符，系统将执行陷阱处理例程来处理异常情况。 否则，系统继续执行代码。 在本发明的一个实施例中，在执行指令之前，系统允许编译器优化包含该指令的程序。 该优化处理包括调度与指令相关联的异常测试指令，以占用指令之后的空闲指令槽。 该异常测试指令确定指令是否导致异常情况。 在本发明的一个实施例中，陷阱处理例程触发回滚操作以撤消由推测线程执行的操作。