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    Low-Voltage, Multiple Thin-Gate Oxide and Low-Resistance Gate Electrode
    11.
    发明申请
    Low-Voltage, Multiple Thin-Gate Oxide and Low-Resistance Gate Electrode 审中-公开
    低电压，多栅极氧化物和低电阻栅极电极

    公开(公告)号：US20070115725A1

    公开(公告)日：2007-05-24

    申请号：US11623947

    申请日：2007-01-17

    申请人： Tuan Pham ,  Masaaki Higashitani

    发明人： Tuan Pham ,  Masaaki Higashitani

    IPC分类号： G11C16/04

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

    摘要： A method of making a memory array and peripheral circuits together on a single substrate forms a dielectric layer, floating gate layer, inter-layer dielectric and mask layer across all regions of the substrate. Subsequently these layers are removed from the peripheral regions and dielectrics of different thicknesses are formed in the peripheral regions according to the voltages of the circuits in these regions. A conductive layer is formed over the memory array and the peripheral circuits to form control gates in the memory array and form gate electrodes in the peripheral regions.

    摘要翻译： 将存储器阵列和外围电路一起制成单个衬底的方法在衬底的所有区域上形成介电层，浮栅，层间电介质和掩模层。 随后，这些层从外围区域移除，并且根据这些区域中的电路的电压在周边区域中形成不同厚度的电介质。 在存储器阵列和外围电路上形成导电层，以在存储器阵列中形成控制栅极并在外围区域中形成栅电极。

    Self Aligned Non-Volatile Memory Cells and Processes for Fabrication
    12.
    发明申请
    Self Aligned Non-Volatile Memory Cells and Processes for Fabrication 有权
    自对准非易失性记忆单元和制造工艺

    公开(公告)号：US20070111422A1

    公开(公告)日：2007-05-17

    申请号：US11622634

    申请日：2007-01-12

    申请人： Jeffrey Lutze ,  Tuan Pham ,  Masaaki Higashitani

    发明人： Jeffrey Lutze ,  Tuan Pham ,  Masaaki Higashitani

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521

    摘要： A non-volatile memory array has word lines coupled to floating gates, the floating gates having an upper portion that is adapted to provide increased surface area, and thereby, to provide increased coupling to the word lines. Shielding between floating gates is also provided. A first process forms floating gates by etching an upper portion of a polysilicon structure with masking elements in place to shape the floating gate. A second process etches recesses and protrusions in a polysilicon structure prior to etching the structure to form individual floating gates.

    摘要翻译： 非易失性存储器阵列具有耦合到浮动栅极的字线，浮动栅极具有适于提供增加的表面积的上部部分，从而提供增加的与字线的耦合。 还提供了浮动门之间的屏蔽。 第一工艺通过用掩蔽元件蚀刻多晶硅结构的上部来形成浮栅来形成浮栅，以形成浮栅。 在蚀刻结构之前，第二工艺蚀刻多晶硅结构中的凹陷和突起以形成单独的浮动栅极。

    Low-voltage, multiple thin-gate oxide and low-resistance gate electrode
    13.
    发明授权
    Low-voltage, multiple thin-gate oxide and low-resistance gate electrode 有权
    低电压，多栅极氧化物和低电阻栅电极

    公开(公告)号：US07202125B2

    公开(公告)日：2007-04-10

    申请号：US11021693

    申请日：2004-12-22

    申请人： Tuan Pham ,  Masaaki Higashitani

    发明人： Tuan Pham ,  Masaaki Higashitani

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

    摘要： A method of making a memory array and peripheral circuits together on a single substrate forms a dielectric layer, floating gate layer, inter-layer dielectric and mask layer across all regions of the substrate. Subsequently these layers are removed from the peripheral regions and dielectrics of different thicknesses are formed in the peripheral regions according to the voltages of the circuits in these regions. A conductive layer is formed over the memory array and the peripheral circuits to form control gates in the memory array and form gate electrodes in the peripheral regions.

    摘要翻译： 将存储器阵列和外围电路一起制成单个衬底的方法在衬底的所有区域上形成介电层，浮栅，层间电介质和掩模层。 随后，这些层从外围区域移除，并且根据这些区域中的电路的电压在周边区域中形成不同厚度的电介质。 在存储器阵列和外围电路上形成导电层，以在存储器阵列中形成控制栅极并在外围区域中形成栅电极。

    Integrated circuits with sidewall nitridation
    14.
    发明授权
    Integrated circuits with sidewall nitridation 有权
    具有侧壁氮化的集成电路

    公开(公告)号：US08853763B2

    公开(公告)日：2014-10-07

    申请号：US13607375

    申请日：2012-09-07

    申请人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

    发明人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

    IPC分类号： H01L29/76 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28

    CPC分类号： H01L27/11548 ,  H01L21/2815 ,  H01L27/11529 ,  H01L29/66825

    摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.

    摘要翻译： 半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。 在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。 在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。 在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。 封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。 在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

    Integrated Circuits With Sidewall Nitridation
    15.
    发明申请
    Integrated Circuits With Sidewall Nitridation 有权
    集成电路与侧壁氮化

    公开(公告)号：US20120326220A1

    公开(公告)日：2012-12-27

    申请号：US13607375

    申请日：2012-09-07

    申请人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

    发明人： Tuan Pham ,  Sanghyun Lee ,  Masato Horiike ,  Klaus Schuegraf ,  Masaaki Higashitani ,  Keiichi Isono

    IPC分类号： H01L29/78

    CPC分类号： H01L27/11548 ,  H01L21/2815 ,  H01L27/11529 ,  H01L29/66825

    摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.

    摘要翻译： 半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。 在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。 在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。 在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。 封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。 在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

    Integrated non-volatile memory and peripheral circuitry fabrication
    17.
    发明授权
    Integrated non-volatile memory and peripheral circuitry fabrication 有权
    集成的非易失性存储器和外围电路制造

    公开(公告)号：US07704832B2

    公开(公告)日：2010-04-27

    申请号：US12058512

    申请日：2008-03-28

    申请人： James Kai ,  Tuan Pham ,  Masaaki Higashitani ,  George Matamis ,  Takashi Orimoto

    发明人： James Kai ,  Tuan Pham ,  Masaaki Higashitani ,  George Matamis ,  Takashi Orimoto

    IPC分类号： H01L21/8247

    CPC分类号： H01L27/11529 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11539

    摘要： Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.

    摘要翻译： 提供非易失性存储器和集成存储器和外围电路制造工艺。 使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。 中间电介质层设置在电荷存储区域的上方。 将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。 从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。 外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。 这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。

    Method of manufacturing self aligned non-volatile memory cells
    18.
    发明授权
    Method of manufacturing self aligned non-volatile memory cells 有权
    制造自对准非易失性存储单元的方法

    公开(公告)号：US07183153B2

    公开(公告)日：2007-02-27

    申请号：US10799060

    申请日：2004-03-12

    申请人： Jeffrey W. Lutze ,  Tuan Pham ,  Masaaki Higashitani

    发明人： Jeffrey W. Lutze ,  Tuan Pham ,  Masaaki Higashitani

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521

    摘要： A method of forming an array of non-volatile memory cells includes forming a plurality of floating gate structures and shaping the plurality of floating gate structures to reduce the width of upper parts of floating gate structures. A first process forms floating gates by etching an upper portion of a polysilicon structure with masking elements in place to shape the floating gate. A second process etches recesses and protrusions in a polysilicon structure prior to etching the structure to form individual floating gates.

    摘要翻译： 形成非易失性存储单元阵列的方法包括形成多个浮置栅极结构并使多个浮动栅极结构成形以减小浮动栅极结构的上部的宽度。 第一工艺通过用掩蔽元件蚀刻多晶硅结构的上部来形成浮栅来形成浮栅，以形成浮栅。 在蚀刻结构之前，第二工艺蚀刻多晶硅结构中的凹陷和突起以形成单独的浮动栅极。

    Multi-thickness dielectric for semiconductor memory
    19.
    发明申请
    Multi-thickness dielectric for semiconductor memory 有权

    公开(公告)号：US20060134864A1

    公开(公告)日：2006-06-22

    申请号：US11020402

    申请日：2004-12-22

    申请人： Masaaki Higashitani ,  Tuan Pham

    发明人： Masaaki Higashitani ,  Tuan Pham

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546

    摘要： A process provides a gate dielectric layer of a first thickness for a memory array and for certain peripheral circuits on the same substrate as the memory array. High-voltage peripheral circuits are provided with a gate dielectric layer of a second thickness. Low-voltage peripheral circuits are provided with a gate dielectric layer of a third thickness. The process provides protection from subsequent process steps for a gate dielectric layer. Shallow trench isolation allows the memory array cells to be extremely small, thus providing high storage density.