公开(公告)号：US20060176201A1

公开(公告)日：2006-08-10

申请号：US11346536

申请日：2006-02-02

申请人： Kenji Kimura ,  Masahiko Mizuta

发明人： Kenji Kimura ,  Masahiko Mizuta

IPC分类号： H03M1/66

CPC分类号： H04N1/40 ,  H04N1/0083

摘要： An analog front-end circuit controlling an imaging device and processing an analog image signal output from the imaging device includes: an analog processing section that receives an analog image signal from the imaging device, provides the image signal with predetermined processing, and outputs the image signal; an A/D converter that performs A/D conversion with the image signal output from the analog processing section; a transmitter circuit that receives digital image data output from the A/D converter, generates a differential signal based on the digital image data, and outputs the differential signal; and a timing generator that generates a plurality of clocks induding a multiphase driving clock for driving the imaging device based on a first reference clock; the transmitter circuit including a differential amplifier circuit that generates a differential signal based on the digital image data output from the A/D converter, and outputting the differential signal generated in the differential amplifier circuit.

摘要翻译： 控制成像装置并处理从成像装置输出的模拟图像信号的模拟前端电路包括：模拟处理部分，其从成像装置接收模拟图像信号，为图像信号提供预定的处理，并输出图像 信号; A / D转换器，其利用从模拟处理部分输出的图像信号进行A / D转换; 接收从A / D转换器输出的数字图像数据的发送电路，根据数字图像数据生成差分信号，并输出差分信号; 以及定时发生器，其产生包含用于基于第一参考时钟驱动所述成像装置的多相驱动时钟的多个时钟; 所述发射机电路包括差分放大器电路，所述差分放大器电路基于从所述A / D转换器输出的数字图像数据产生差分信号，并输出在差分放大器电路中产生的差分信号。

公开(公告)号：US20050205488A1

公开(公告)日：2005-09-22

申请号：US11125179

申请日：2005-05-10

申请人： Katsuhiko Shinada ,  Kei Murase ,  Teruyuki Yamada ,  Yuuichi Shirasu ,  Masahiko Mizuta ,  Hiroyuki Fujiki

发明人： Katsuhiko Shinada ,  Kei Murase ,  Teruyuki Yamada ,  Yuuichi Shirasu ,  Masahiko Mizuta ,  Hiroyuki Fujiki

IPC分类号： B01D29/00 ,  B01D67/00 ,  B01D69/08 ,  B01D69/10 ,  B01D69/12 ,  B01D71/34

CPC分类号： B01D69/08 ,  B01D67/0011 ,  B01D69/087 ,  B01D69/10 ,  B01D69/12 ,  B01D71/34 ,  B01D2325/02 ,  B01D2325/023 ,  B01D2325/24

摘要： An object of the present invention is to provide a composite porous membrane, which has not only excellent filtration capacity, but also excellent adhesion between a porous membrane and a braid and mechanical properties, and a method for producing the composite porous membrane. The present invention relates to a composite porous membrane comprising a braid, and a membrane material; wherein the membrane material comprises a first porous layer comprising a dense layer which is arranged on the outer surface of the braid, and a second porous layer comprising a dense layer which is arranged on the first porous layer, and a method for producing the composite porous membrane.

摘要翻译： 本发明的目的是提供一种复合多孔膜，其不仅具有优异的过滤能力，而且具有多孔膜与编织物之间的优异粘合性和机械性能，以及复合多孔膜的制造方法。 本发明涉及一种复合多孔膜，包括编织物和膜材料; 其中所述膜材料包括布置在所述编织物的外表面上的致密层的第一多孔层和布置在所述第一多孔层上的致密层的第二多孔层以及所述复合多孔层的制造方法 膜。

公开(公告)号：US06416576B1

公开(公告)日：2002-07-09

申请号：US09864936

申请日：2001-05-25

申请人： Masahiko Mizuta ,  Tokuji Maeda ,  Masato Tabuchi

发明人： Masahiko Mizuta ,  Tokuji Maeda ,  Masato Tabuchi

IPC分类号： C30B1520

CPC分类号： C30B29/06 ,  C30B15/26

摘要： In pulling a single crystal by CZ method, stable pulling up is carried out in a pulling rate as fast as possible while a crystal deformation is controlled to an aimed value and density of grown-in defects is suppressed to a value below an upper limit value. As an index of deformation of the single crystal from a perfect circle, the aimed value of the crystal deformation is previously determined. The upper limit value of a pulling rate necessary to suppress a defect density to an allowable range is previously calculated from distribution of grown-in defects in the crystal section, the single crystal is pulled up according to a predetermined pulling rate, and then deviation of the achieved value from the aimed value of the crystal deformation in pulling is calculated. The deviation is converted to a correction of the pulling rate. This correction is added to a set value of the pulling rate in the pulling and the result is used as a temporary set value of the pulling rate in the next pulling. The temporary set value is compared with the upper limit value of the above described pulling rate and the smaller value is determined as the pulling rate in the next runs.

摘要翻译： 在通过CZ法拉取单晶时，以尽可能快的拉伸速度进行稳定的拉伸，同时将晶体变形控制为目标值，并且将生长的缺陷的密度抑制在低于上限值的值 。 作为单晶从正圆变形的指标，预先确定晶体变形的目标值。 将缺陷密度抑制到容许范围所需的拉拔速度的上限值是从晶体截面中的生长缺陷的分布预先计算出来的，单晶根据规定的拉伸速度被拉起，然后偏离 计算从牵引中的晶体变形的目标值得到的值。 该偏差被转换为拉动速率的校正。 将该校正加到牵引中的拉动速度的设定值，将结果作为下次牵引中的牵引速度的临时设定值。 将临时设定值与上述牵引速度的上限值进行比较，并将较小的值确定为下次运行中的牵引速率。

公开(公告)号：US09296886B2

公开(公告)日：2016-03-29

申请号：US14112237

申请日：2012-04-19

申请人： Katsuhiko Shinada ,  Masahiko Mizuta

发明人： Katsuhiko Shinada ,  Masahiko Mizuta

IPC分类号： D01D1/04 ,  D01F6/76 ,  C08L27/16 ,  C08J3/09

CPC分类号： C08L27/16 ,  C08J3/09 ,  C08J2300/00 ,  C08J2327/08 ,  C08J2339/06

摘要： A method for dissolving and degassing a polymer is described, including a dissolution/degassing step. In the dissolution/degassing step, a mixture containing the polymer and a solvent is agitated, in a pressure-reduced condition with a gauge pressure of −50 to −90 kPa and at a temperature lower than the boiling point of the solvent in the pressure-reduced condition but higher than the freezing point of the same, to dissolve the polymer and simultaneously degas the polymer solution, so as to obtain a polymer solution.

摘要翻译： 描述了一种溶解和脱气聚合物的方法，包括溶解/脱气步骤。 在溶解/脱气步骤中，在压力为-50至-90kPa的压力降压条件下，在低于溶剂沸点的压力下，搅拌含有聚合物和溶剂的混合物 降低的条件但高于其凝固点，以溶解聚合物并同时使聚合物溶液脱气，从而获得聚合物溶液。

公开(公告)号：US07999975B2

公开(公告)日：2011-08-16

申请号：US12149780

申请日：2008-05-08

申请人： Masahiko Mizuta

发明人： Masahiko Mizuta

IPC分类号： H04N1/40 ,  H04N1/46

CPC分类号： H04N1/48 ,  H01L27/14623 ,  H04N1/1008 ,  H04N1/193 ,  H04N5/361 ,  H04N5/378 ,  H04N2201/0093

摘要： An analog front-end circuit includes an analog processing circuit, an A/D converter, a calculation circuit, and a target register in which a black level target value is set. The analog processing circuit includes a clamp circuit that performs a line clamp operation, and an offset adjustment circuit. The calculation circuit monitors an A/D-converted value of a black reference pixel after the line clamp operation in a black level monitor period after a line clamp period but before an effective pixel output period, and performs a black level error correction process by writing an offset adjustment value that causes the A/D-converted value to be set at the black level target value into the offset adjustment register.

摘要翻译： 模拟前端电路包括模拟处理电路，A / D转换器，计算电路和设定黑电平目标值的目标寄存器。 模拟处理电路包括执行线路钳位操作的钳位电路和偏移调整电路。 计算电路在线路钳位期间之后但在有效像素输出期间之前的黑电平监视期间内对线路钳位动作后的黑色参考像素的A / D转换值进行监视，并通过写入进行黑电平纠错处理 将A / D转换值设定为黑电平目标值的偏移调整值输入偏移调整寄存器。

公开(公告)号：US20090009618A1

公开(公告)日：2009-01-08

申请号：US12070317

申请日：2008-02-18

申请人： Tomonaga Hasegawa ,  Masahiko Mizuta

发明人： Tomonaga Hasegawa ,  Masahiko Mizuta

IPC分类号： H04N5/228

CPC分类号： H04N5/335 ,  H04N5/3765

摘要： An analog front-end circuit includes an analog processing circuit, an A/D converter, and a timing generator that generates a plurality of control signals that are supplied to an image sensor. The timing generator includes an event information memory, and a control signal output circuit that generates the control signals based on information read from the event information memory and outputs the generated control signals. The event information memory stores a pixel number and change event occurrence information at each address. The change event occurrence information specifies a control signal that undergoes a signal level change event at the pixel number. The control signal output circuit generates the control signals based on the pixel number and the change event occurrence information read from the event information memory and outputs the generated control signals.

摘要翻译： 模拟前端电路包括模拟处理电路，A / D转换器和产生提供给图像传感器的多个控制信号的定时发生器。 定时发生器包括事件信息存储器和控制信号输出电路，其根据从事件信息存储器读取的信息产生控制信号，并输出所生成的控制信号。 事件信息存储器存储每个地址处的像素数和改变事件发生信息。 改变事件发生信息指定在像素数处经历信号电平变化事件的控制信号。 控制信号输出电路基于从事件信息存储器读取的像素数和变化事件发生信息生成控制信号，并输出所生成的控制信号。

公开(公告)号：US07306105B2

公开(公告)日：2007-12-11

申请号：US11125179

申请日：2005-05-10

申请人： Katsuhiko Shinada ,  Kei Murase ,  Teruyuki Yamada ,  Yuuichi Shirasu ,  Masahiko Mizuta ,  Hiroyuki Fujiki

发明人： Katsuhiko Shinada ,  Kei Murase ,  Teruyuki Yamada ,  Yuuichi Shirasu ,  Masahiko Mizuta ,  Hiroyuki Fujiki

IPC分类号： B01D69/12 ,  B01D69/10 ,  B01D29/00

CPC分类号： B01D69/08 ,  B01D67/0011 ,  B01D69/087 ,  B01D69/10 ,  B01D69/12 ,  B01D71/34 ,  B01D2325/02 ,  B01D2325/023 ,  B01D2325/24

摘要： An object of the present invention is to provide a composite porous membrane, which has not only excellent filtration capacity, but also excellent adhesion between a porous membrane and a braid and mechanical properties, and a method for producing the composite porous membrane. The present invention relates to a composite porous membrane comprising a braid, and a membrane material; wherein the membrane material comprises a first porous layer comprising a dense layer which is arranged on the outer surface of the braid, and a second porous layer comprising a dense layer which is arranged on the first porous layer, and a method for producing the composite porous membrane.

公开(公告)号：US20060176525A1

公开(公告)日：2006-08-10

申请号：US11347686

申请日：2006-02-03

申请人： Masahiko Mizuta ,  Kenji Kimura

发明人： Masahiko Mizuta ,  Kenji Kimura

IPC分类号： H04N1/04

CPC分类号： H04N1/0473 ,  H04N1/1013 ,  H04N1/192 ,  H04N2201/0477 ,  H04N2201/04774

摘要： An analog front-end circuit that controls an imaging device and processes an analog image signal output from the imaging device comprises: an analog processor that receives an analog image signal from the imaging device, provides the image signal with predetermined processing, and outputs a resultant signal; an A/D converter that performs A/D conversion with the image signal output from the analog processor; a holding circuit that holds digital image data output from the A/D converter; a timing generator that, based on a first reference clock, generates a plurality of clocks and outputs the clocks to at least one of the analog processor and the A/D converter; and a spread spectrum modulation circuit that performs spread spectrum modulation with the first reference clock and outputs a resultant clock that has been subject to the spread spectrum modulation as a modulated clock to the holding circuit; wherein the holding circuit holds the digital image data from the A/D converter based on the modulated clock output from the spread spectrum modulation circuit.

摘要翻译： 控制成像装置并处理从成像装置输出的模拟图像信号的模拟前端电路包括：模拟处理器，其从成像装置接收模拟图像信号，以预定的处理提供图像信号，并输出结果 信号; A / D转换器，利用从模拟处理器输出的图像信号进行A / D转换; 保持电路，其保持从A / D转换器输出的数字图像数据; 定时发生器，其基于第一参考时钟产生多个时钟，并且将所述时钟输出到所述模拟处理器和所述A / D转换器中的至少一个; 以及扩频调制电路，其利用所述第一参考时钟进行扩频调制，并将经过所述扩频调制的合成时钟作为调制时钟输出到所述保持电路; 其中保持电路基于从扩展频谱调制电路输出的调制时钟保持来自A / D转换器的数字图像数据。