公开(公告)号：US20120229197A1

公开(公告)日：2012-09-13

申请号：US13369063

申请日：2012-02-08

申请人： Masahiro ARAKI ,  Atsuhiko Ishibashi

发明人： Masahiro ARAKI ,  Atsuhiko Ishibashi

IPC分类号： G11C5/14

CPC分类号： G11C7/1057 ,  G11C13/0002

摘要： The present invention provides a semiconductor device in which an adjustable range of a resistance value of a variable resistance circuit is large. The semiconductor device has an output buffer including a plurality of sets of resistance elements and a plurality of sets of transistors, a plurality of replica circuits, and a plurality of sets of operational amplifiers, and drain currents of the plurality of sets of transistors are adjusted so that output impedances of the output buffer become predetermined values. Therefore, even in the case where the resistance values of the resistance elements largely fluctuate due to fluctuations in manufacture process and the like, the output impedances can be set to predetermined values.

摘要翻译： 本发明提供一种半导体器件，其中可变电阻电路的电阻值的可调范围大。 半导体器件具有包括多组电阻元件和多组晶体管，多个复制电路和多组运算放大器的输出缓冲器，并且调节多组晶体管的漏极电流 使得输出缓冲器的输出阻抗变为预定值。 因此，即使在电阻元件的电阻值由于制造工艺等的波动而大幅波动的情况下，也可以将输出阻抗设定为规定值。

公开(公告)号：US07397269B2

公开(公告)日：2008-07-08

申请号：US11730987

申请日：2007-04-05

申请人： Atsuhiko Ishibashi ,  Yasuhiro Fujino

发明人： Atsuhiko Ishibashi ,  Yasuhiro Fujino

IPC分类号： H03K19/007

CPC分类号： G01R31/025 ,  G01R31/317 ,  H03K3/037

摘要： Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted from a PADI and an inverting clock signal inputted from a PADR; a second comparator to compare a non-inverting clock signal and a reference potential Vref; and a third comparator to compare an inverting clock signal and the reference potential Vref. Their respective outputs are defined as Y, YI and YR, respectively. If the signal line of either a non-inverting clock signal or an inverting clock signal is disconnected, or short-circuited to a grounding potential VSS of a logical value Low, the logical values outputted from the second and the third comparators are equal for a long period of time in one cycle of the non-inverting clock signal or the inverting clock signal. Thereby, if a second D-flip-flop circuit F2a negates an output signal [CD], it is able to judge that disconnection or short occurs.

摘要翻译： 提供了能够检测发送差分时钟信号的信号线的断开和短路的断开和短路检测电路。 差分缓冲器部分DB1具有第一比较器，用于比较从PADI输入的非反相时钟信号和从PADR输入的反相时钟信号; 第二比较器，用于比较非反相时钟信号和参考电位Vref; 以及比较反相时钟信号和参考电位Vref的第三比较器。 它们各自的输出分别定义为Y，YI和YR。 如果非反相时钟信号或反相时钟信号的信号线断开或短路到逻辑值Low的接地电位VSS，则从第二和第三比较器输出的逻辑值对于 长时间在一个周期的非反相时钟信号或反相时钟信号。 因此，如果第二D触发器电路F 2 a否定输出信号[CD]，则能够判断出断开或短路。

公开(公告)号：US5945883A

公开(公告)日：1999-08-31

申请号：US986323

申请日：1997-12-05

申请人： Hideaki Nagasawa ,  Atsuhiko Ishibashi

发明人： Hideaki Nagasawa ,  Atsuhiko Ishibashi

IPC分类号： H03K3/011 ,  H03K3/03 ,  H03K3/354 ,  H03B5/04

CPC分类号： H03K3/354 ,  H03K3/011 ,  H03K3/0315

摘要： A circuit for suppressing period jitter of the clock output of a ring oscillator caused by supply voltage fluctuations. The ring oscillator includes n identical current controlled delay circuits 26.1-n connected in a ring, and a replica circuit 36 identical to the current controlled delay circuit. The replica circuit 36 receives a constant input voltage so that its output is always at a high level. A differential amplifier 35 receiving a reference potential Vref is connected in a negative feedback circuit with replica circuit 36, so that the output of the replica circuit 36 is held equal to the reference potential Vref. An output of the negative feedback circuit is also applied to each of the current controlled delay circuits 26.1-n, so that their high level outputs are held equal to the reference potential Vref.

摘要翻译： 用于抑制由电源电压波动引起的环形振荡器的时钟输出的周期抖动的电路。 环形振荡器包括以环形连接的n个相同的电流控制延迟电路26.1-n和与当前受控延迟电路相同的复制电路36。 复制电路36接收恒定的输入电压，使其输出始终处于高电平。 接收参考电位Vref的差分放大器35在负反馈电路中与复制电路36连接，使得复制电路36的输出保持等于参考电位Vref。 负反馈电路的输出也被施加到每个电流控制延迟电路26.1-n，使得它们的高电平输出保持等于参考电位Vref。

公开(公告)号：US20100177814A1

公开(公告)日：2010-07-15

申请号：US12730061

申请日：2010-03-23

申请人： Hideki UCHIKI ,  Atsuhiko Ishibashi

发明人： Hideki UCHIKI ,  Atsuhiko Ishibashi

IPC分类号： H04L27/01

CPC分类号： H04L25/03878

摘要： The present invention provides an equalizer and a semiconductor device, that can suppress a decrease in S/N ratio of a reception signal, can facilitate a disconnection test by a direct current signal, and are excellent in reproducibility of a transmission signal. A low-pass filter receives a reception signal supplied from a reception end to output a signal obtained by removing a high frequency component from the reception signal. A subtraction unit subtracts an output signal from the low-pass filter from the reception signal. An addition unit adds the reception signal from the reception end to an output signal from the subtraction unit. Thus, an output signal from the addition unit has a frequency characteristic of emphasizing the high frequency component. Then, an amplifier amplifies the output signal from the addition unit to transmit it to an output end.

摘要翻译： 本发明提供了一种可以抑制接收信号的S / N比的降低的均衡器和半导体器件，可以促进直流信号的断开测试，并且传输信号的再现性优异。 低通滤波器接收从接收端提供的接收信号，以从接收信号输出从高频分量中去除的信号。 减法单元从接收信号中减去低通滤波器的输出信号。 加法单元将来自接收端的接收信号与来自减法单元的输出信号相加。 因此，来自加法单元的输出信号具有强调高频分量的频率特性。 然后，放大器放大来自加法单元的输出信号，将其发送到输出端。

公开(公告)号：US20070296455A1

公开(公告)日：2007-12-27

申请号：US11730987

申请日：2007-04-05

申请人： Atsuhiko Ishibashi ,  Yasuhiro Fujino

发明人： Atsuhiko Ishibashi ,  Yasuhiro Fujino

IPC分类号： H03K19/007

CPC分类号： G01R31/025 ,  G01R31/317 ,  H03K3/037

摘要： Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted from a PADI and an inverting clock signal inputted from a PADR; a second comparator to compare a non-inverting clock signal and a reference potential Vref; and a third comparator to compare an inverting clock signal and the reference potential Vref. Their respective outputs are defined as Y, YI and YR, respectively. If the signal line of either a non-inverting clock signal or an inverting clock signal is disconnected, or short-circuited to a grounding potential VSS of a logical value Low, the logical values outputted from the second and the third comparators are equal for a long period of time in one cycle of the non-inverting clock signal or the inverting clock signal. Thereby, if a second D-flip-flop circuit F2a negates an output signal [CD], it is able to judge that disconnection or short occurs.

摘要翻译： 提供了能够检测发送差分时钟信号的信号线的断开和短路的断开和短路检测电路。 差分缓冲器部分DB1具有第一比较器，用于比较从PADI输入的非反相时钟信号和从PADR输入的反相时钟信号; 第二比较器，用于比较非反相时钟信号和参考电位Vref; 以及比较反相时钟信号和参考电位Vref的第三比较器。 它们各自的输出分别定义为Y，YI和YR。 如果非反相时钟信号或反相时钟信号的信号线断开或短路到逻辑值Low的接地电位VSS，则从第二和第三比较器输出的逻辑值对于 长时间在一个周期的非反相时钟信号或反相时钟信号。 因此，如果第二D触发器电路F 2 a否定输出信号[CD]，则能够判断出断开或短路。

公开(公告)号：US07212027B2

公开(公告)日：2007-05-01

申请号：US10900312

申请日：2004-07-28

申请人： Atsuhiko Ishibashi ,  Yasuhiro Fujino

发明人： Atsuhiko Ishibashi ,  Yasuhiro Fujino

IPC分类号： H03K19/007

CPC分类号： G01R31/025 ,  G01R31/317 ,  H03K3/037

摘要： Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted from a PADI and an inverting clock signal inputted from a PADR; a second comparator to compare a non-inverting clock signal and a reference potential Vref; and a third comparator to compare an inverting clock signal and the reference potential Vref. Their respective outputs are defined as Y, YI and YR, respectively. If the signal line of either a non-inverting clock signal or an inverting clock signal is disconnected, or short-circuited to a grounding potential VSS of a logical value Low, the logical values outputted from the second and the third comparators are equal for a long period of time in one cycle of the non-inverting clock signal or the inverting clock signal. Thereby, if a second D-flip-flop circuit F2a negates an output signal [CD], it is able to judge that disconnection or short occurs.

摘要翻译： 提供了能够检测发送差分时钟信号的信号线的断开和短路的断开和短路检测电路。 差分缓冲器部分DB1具有第一比较器，用于比较从PADI输入的非反相时钟信号和从PADR输入的反相时钟信号; 第二比较器，用于比较非反相时钟信号和参考电位Vref; 以及比较反相时钟信号和参考电位Vref的第三比较器。 它们各自的输出分别定义为Y，YI和YR。 如果非反相时钟信号或反相时钟信号的信号线断开或短路到逻辑值Low的接地电位VSS，则从第二和第三比较器输出的逻辑值对于 长时间在一个周期的非反相时钟信号或反相时钟信号。 因此，如果第二D触发器电路F 2 a否定输出信号[CD]，则能够判断出断开或短路。

公开(公告)号：US5764110A

公开(公告)日：1998-06-09

申请号：US769801

申请日：1996-12-20

申请人： Atsuhiko Ishibashi

发明人： Atsuhiko Ishibashi

IPC分类号： H03B1/00 ,  H03K3/011 ,  H03K3/03 ,  H03K3/354 ,  H03L1/00 ,  H03B5/04

CPC分类号： H03K3/0315 ,  H03K3/011 ,  H03K3/354 ,  H03L1/00 ,  H03B2201/02

摘要： A circuit for suppressing period jitter of the clock output of a ring oscillator caused by supply voltage fluctuations. The ring oscillator includes n identical current controlled delay circuits 26.1-n connected in a ring, and a replica circuit 36 identical to the current controlled delay circuit. The replica circuit 36 receives a constant input voltage so that its output is always at a high level. A differential amplifier 35 receiving a reference potential Vref is connected in a negative feedback circuit with replica circuit 36, so that the output of the replica circuit 36 is held equal to the reference potential Vref. An output of the negative feedback circuit is also applied to each of the current controlled delay circuits 26.1-n, so that their high level outputs are held equal to the reference potential Vref.

公开(公告)号：US5694076A

公开(公告)日：1997-12-02

申请号：US622269

申请日：1996-03-27

申请人： Atsuhiko Ishibashi

发明人： Atsuhiko Ishibashi

IPC分类号： H03K19/00 ,  G05F1/46 ,  H03F3/45 ,  G05F1/10

CPC分类号： G05F1/465

摘要： An NMOS transistor (2) has a source electrode, a drain electrode and a gate electrode which are connected to a power source (VSS), an output terminal of a stepdown circuit (27), and a node (N2) between load elements (11, 12) respectively. The transistor size of the NMOS transistor (2) is so set that its drain current exerts no influence on fluctuation of an output voltage (VDD2) when an output voltage control operation by a differential amplification circuit (29) and the stepdown circuit (27) is functional to enable suppression of fluctuation of the output voltage (VDD2), while the output voltage (VDD2) is stepped down on the basis of the current quantity of the drain current of the NMOS transistor (2) when the output voltage control operation is unfunctional to disable suppression of fluctuation of the output voltage (VDD2). Thus, obtained is a voltage generation circuit which can reliably suppress fluctuation of the output voltage regardless of the frequency of fluctuation in source voltage.

摘要翻译： NMOS晶体管（2）具有连接到电源（VSS）的源电极，漏电极和栅电极，降压电路（27）的输出端子和负载元件之间的节点（N2） 11,12）。 NMOS晶体管（2）的晶体管尺寸设定为当差分放大电路（29）和降压电路（27）的输出电压控制操作时，其漏极电流对输出电压（VDD2）的波动不产生影响， 功能是为了抑制输出电压（VDD2）的波动，同时当输出电压控制操作是基于NMOS晶体管（2）的漏极电流的电流量而输出电压（VDD2）被降低时 无法禁止抑制输出电压的波动（VDD2）。 因此，获得的是能够可靠地抑制输出电压的波动的电压产生电路，而与源极电压的波动频率无关。

公开(公告)号：US5374904A

公开(公告)日：1994-12-20

申请号：US79755

申请日：1993-06-22

申请人： Atsuhiko Ishibashi

发明人： Atsuhiko Ishibashi

IPC分类号： H03L7/093 ,  H03L7/099 ,  H03L7/085

CPC分类号： H03L7/093 ,  H03L7/0995

摘要： A phase synchronization circuit including a phase-locked-loop synchronizes a phase of a clock signal with a phase of a reference clock signal having a frequency desired by a user. The gates of an NMOS transistor and a PMOS transistors are connected in common to a resistor. The drain and the source of the NMOS transistor are both connected to a ground potential while the drain and the source of the PMOS transistor are both connected to a power source voltage. By changing a number of NMOS and PMOS transistors formed during a metallization process, the capacitance in a loop filter is easily changed.

摘要翻译： 包括锁相环的相位同步电路使时钟信号的相位与具有用户期望的频率的参考时钟信号的相位同步。 NMOS晶体管和PMOS晶体管的栅极共同连接到电阻器。 NMOS晶体管的漏极和源极都连接到地电位，而PMOS晶体管的漏极和源极都连接到电源电压。 通过改变在金属化处理期间形成的多个NMOS和PMOS晶体管，环路滤波器中的电容容易改变。

公开(公告)号：US08350609B2

公开(公告)日：2013-01-08

申请号：US13369063

申请日：2012-02-08

申请人： Masahiro Araki ,  Atsuhiko Ishibashi

发明人： Masahiro Araki ,  Atsuhiko Ishibashi

IPC分类号： H03K5/12

CPC分类号： G11C7/1057 ,  G11C13/0002

摘要： The present invention provides a semiconductor device in which an adjustable range of a resistance value of a variable resistance circuit is large. The semiconductor device has an output buffer including a plurality of sets of resistance elements and a plurality of sets of transistors, a plurality of replica circuits, and a plurality of sets of operational amplifiers, and drain currents of the plurality of sets of transistors are adjusted so that output impedances of the output buffer become predetermined values. Therefore, even in the case where the resistance values of the resistance elements largely fluctuate due to fluctuations in manufacture process and the like, the output impedances can be set to predetermined values.

摘要翻译： 本发明提供一种半导体器件，其中可变电阻电路的电阻值的可调范围大。 半导体器件具有包括多组电阻元件和多组晶体管，多个复制电路和多组运算放大器的输出缓冲器，并且调节多组晶体管的漏极电流 使得输出缓冲器的输出阻抗变为预定值。 因此，即使在电阻元件的电阻值由于制造工艺等的波动而大幅波动的情况下，也可以将输出阻抗设定为规定值。