公开(公告)号：US06750555B2

公开(公告)日：2004-06-15

申请号：US10263914

申请日：2002-10-03

申请人： Katsuji Satomi ,  Hiroyuki Yamauchi

发明人： Katsuji Satomi ,  Hiroyuki Yamauchi

IPC分类号： H01L2711

CPC分类号： H01L27/1104

摘要： A semiconductor memory device has a SRAM memory cell comprising: a first inverter including a first nMOS transistor and a first pMOS transistor; a second inverter including a second nMOS transistor and a second pMOS transistor; a third nMOS transistor; and a fourth nMOS transistor, wherein a first diffusion region forming the first and third nMOS transistors and a second diffusion region forming the second and fourth nMOS transistors, respectively, are arranged in linear shapes without having any bent part, and driving capabilities of the first and second nMOS transistors are higher than those of the third and fourth nMOS transistors.

摘要翻译： 半导体存储器件具有SRAM存储单元，其包括：第一反相器，包括第一nMOS晶体管和第一pMOS晶体管; 包括第二nMOS晶体管和第二pMOS晶体管的第二反相器; 第三个nMOS晶体管; 以及第四nMOS晶体管，其中分别形成所述第一和第三nMOS晶体管的第一扩散区域和形成所述第二和第四nMOS晶体管的第二扩散区域被布置成线形，而没有任何弯曲部分，并且所述第一扩散区域的驱动能力 并且第二nMOS晶体管高于第三和第四nMOS晶体管的晶体管。

公开(公告)号：US06604201B1

公开(公告)日：2003-08-05

申请号：US09428277

申请日：1999-10-27

申请人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Tadahiro Yoshida ,  Yutaka Terada ,  Yukio Arima ,  Takashi Hirata ,  Yoshihide Komatsu

发明人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Tadahiro Yoshida ,  Yutaka Terada ,  Yukio Arima ,  Takashi Hirata ,  Yoshihide Komatsu

IPC分类号： G06F132

CPC分类号： H04L12/12 ,  Y02D50/20 ,  Y02D50/40

摘要： A power-saving network unit, which is connected to a network made up of a plurality of power-saving network units, includes: network monitoring means; network information memory; power-saving mode setting means; peripheral I/O interface; and digital processor. The network monitoring means monitors a topology of the network, or the interconnection relationship among the power-saving network units. Every time the network has been modified, the network monitoring means stores the modified network topology on the network information memory. The power-saving mode setting means receives the network information stored on the network information memory. If the power-saving network unit is a master or relay node in the network, then the power-saving mode setting means locks the peripheral I/O interface and digital processor of the power-saving network unit to the normal operation mode and prohibits these sections from entering the power-saving mode.

摘要翻译： 连接到由多个省电网络单元组成的网络的节电网单元包括：网络监控装置; 网络信息记忆; 省电模式设定手段; 外设I / O接口; 和数字处理器。 网络监控装置监控网络的拓扑结构，或节能网络单元之间的互连关系。 每当网络被修改时，网络监控装置将修改的网络拓扑存储在网络信息存储器上。 省电模式设置装置接收存储在网络信息存储器上的网络信息。 如果省电网络单元是网络中的主节点或中继节点，则省电模式设置装置将节电网络单元的外围I / O接口和数字处理器锁定到正常操作模式，并禁止这些 部分进入省电模式。

公开(公告)号：US06426985B1

公开(公告)日：2002-07-30

申请号：US09283888

申请日：1999-04-01

申请人： Toru Iwata ,  Hiroyuki Yamauchi

发明人： Toru Iwata ,  Hiroyuki Yamauchi

IPC分类号： H04L700

CPC分类号： H03L7/0814 ,  H03L7/07 ,  H03L7/0818

摘要： A variable delay circuit includes a plurality of delay circuits for delaying an input signal; and a selection circuit for selecting an output from one of the plurality of delay circuits in accordance with a selection signal. The plurality of delay circuits include a first delay circuit for delaying the input signal by a first delay time period and a second delay circuit for delaying the input signal by a second delay time period which is longer than the first delay time period. The difference between the first delay time period and the second delay time period is shorter than a minimum delay time period which is allowed to be set in the first delay circuit.

摘要翻译： 可变延迟电路包括用于延迟输入信号的多个延迟电路; 以及选择电路，用于根据选择信号选择多个延迟电路之一的输出。 多个延迟电路包括用于将输入信号延迟第一延迟时间段的第一延迟电路和用于将输入信号延迟比第一延迟时间段长的第二延迟时间段的第二延迟电路。 第一延迟时间段和第二延迟时间段之间的差值比允许在第一延迟电路中设置的最小延迟时间段短。

公开(公告)号：US06255863B1

公开(公告)日：2001-07-03

申请号：US09573827

申请日：2000-05-18

申请人： Hiroyuki Yamauchi ,  Yutaka Terada

发明人： Hiroyuki Yamauchi ,  Yutaka Terada

IPC分类号： H03K522

CPC分类号： H04L25/0272 ,  H03K5/007 ,  H03K5/082 ,  H03K5/2481 ,  H04L25/028 ,  H04L25/062

摘要： The level of a differential signal is determined such that a system, utilizing the level determined, can operate stably enough even if the intermediate potential of the signal changes. A comparator receives, as differential input, a differential signal to be transmitted. During a level determination interval, a sampler/level determiner samples the output of the comparator a number of times, and outputs a most frequently sampled value as the level of the differential signal.

摘要翻译： 确定差分信号的电平，使得即使信号的中间电位改变，利用所确定的电平的系统也能够稳定地工作。 比较器作为差分输入端接收待发送的差分信号。 在电平确定间隔期间，采样器/电平确定器多次对比较器的输出进行采样，并输出最频繁采样的值作为差分信号的电平。

公开(公告)号：US06246724B1

公开(公告)日：2001-06-12

申请号：US09533982

申请日：2000-03-23

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： H04L2534

CPC分类号： H04L5/20 ,  H04L25/49

摘要： A signal transfer method for transferring a multi-bit signal over a transfer path which is allocated to one bit includes the steps of: respectively assigning a plurality of parameters for a plurality of bits so that a value representing “0” or a value representing “1” is set to each of the plurality of parameters in accordance with a value of a corresponding one of the plurality of bits; outputting an electric signal to the transfer path, the electric signal expressing a combination of the plurality of parameters having the values as set in the assigning step; receiving the electric signal from the transfer path and extracting the plurality of parameters from the electric signal; and detecting the respective values of the plurality of parameters.

摘要翻译： 用于通过分配给一位的传送路径传送多位信号的信号传送方法包括以下步骤：分别分配多个比特的多个参数，使得表示“0”的值或表示“ 1“根据多个比特中的相应一个比特的值被设置为多个参数中的每一个; 向所述传送路径输出电信号，所述电信号表示具有在所述分配步骤中设定的值的所述多个参数的组合; 从传输路径接收电信号并从电信号中提取多个参数; 以及检测所述多个参数的相应值。

公开(公告)号：US06208567B1

公开(公告)日：2001-03-27

申请号：US09014775

申请日：1998-01-28

申请人： Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Toru Iwata ,  Keiichi Kusumoto ,  Satoshi Takahashi ,  Yutaka Terada ,  Takashi Hirata

发明人： Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Toru Iwata ,  Keiichi Kusumoto ,  Satoshi Takahashi ,  Yutaka Terada ,  Takashi Hirata

IPC分类号： G11C2900

CPC分类号： G01R31/3004 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.

摘要翻译： 本发明的半导体器件包括：包括多个电路块的阵列部分; 泄漏电流切断部，切断在所述阵列部中的所述多个电路块中的至少一个电路中发生的漏电流; 以及控制部分，用于根据泄漏电流切断信息控制漏电流切断部分。

公开(公告)号：US06194926B1

公开(公告)日：2001-02-27

申请号：US09291173

申请日：1999-04-14

申请人： Satoshi Takahashi ,  Hiroyuki Yamauchi

发明人： Satoshi Takahashi ,  Hiroyuki Yamauchi

IPC分类号： H03L700

CPC分类号： H03L7/00 ,  G06F1/04

摘要： A system of the type including a plurality of circuit blocks is provided with an operation timing controller for controlling the operation timing of these circuit blocks by supplying associated operation control signals thereto. The operation timing controller includes a memory for memorizing respective times when a peak current state arises in these circuit blocks, thereby controlling the timing of the operation control signals in accordance with the memorized times when the peak current state arises. As a result, coincident switching noise can be suppressed no matter when the peak current state arises in these circuit blocks.

摘要翻译： 包括多个电路块的类型的系统设置有操作定时控制器，用于通过向其提供相关联的操作控制信号来控制这些电路块的操作定时。 操作定时控制器包括用于在这些电路块中出现峰值电流状态时存储各个时间的存储器，从而根据当峰值电流状态出现时的存储时间来控制操作控制信号的定时。 结果，无论何时在这些电路块中出现峰值电流状态，也可以抑制一致的开关噪声。

公开(公告)号：US6127950A

公开(公告)日：2000-10-03

申请号：US244764

申请日：1999-02-05

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： H03M7/00

CPC分类号： H03M5/145

摘要： Image data is transmitted from a memory to a CPU (central processing unit). A transmission circuit of the memory receives an 8-bit source parallel signal, makes reference to transmission histories or to transmission predictions to generate a 2-bit coded parallel signal from the source parallel signal, and sends a serial signal as a result of converting the coded parallel signal, together with a flag signal indicative of the presence of an encoding. If the source parallel signal remains unchanged, the coded parallel signal is made to indicate 00 so that the bit transition probability of the serial signal is reduced. A reception circuit of the CPU receives the serial and flag signals and restores the 8-bit source parallel signal on the basis of reception histories or on the basis of reception predictions. If the transmission circuit fails in performing an encoding, then a serial signal as a result of directly converting the source parallel signal is sent together with a flag signal indicative of the absence of an encoding.

摘要翻译： 图像数据从存储器发送到CPU（中央处理单元）。 存储器的发送电路接收8位源并行信号，参照发送历史或发送预测，从源并行信号生成2比特编码并行信号，作为转换结果的结果发送串行信号 编码并行信号，以及指示编码存在的标志信号。 如果源并行信号保持不变，则将编码的并行信号指示为00，使得串行信号的位转移概率减小。 CPU的接收电路接收串行和标志信号，并根据接收历史或基于接收预测恢复8位源并行信号。 如果发送电路执行编码失败，则作为直接转换源并行信号的结果的串行信号与指示不存在编码的标志信号一起发送。

公开(公告)号：US5999022A

公开(公告)日：1999-12-07

申请号：US631914

申请日：1996-04-15

申请人： Toru Iwata ,  Hironori Akamatsu ,  Hisakazu Kotani ,  Hiroyuki Yamauchi ,  Akira Matsuzawa ,  Shoichiro Tada

发明人： Toru Iwata ,  Hironori Akamatsu ,  Hisakazu Kotani ,  Hiroyuki Yamauchi ,  Akira Matsuzawa ,  Shoichiro Tada

IPC分类号： H03K19/00 ,  H03K19/0185 ,  H03K3/00

CPC分类号： H03K19/01855 ,  H03K19/0016

摘要： A driver circuit which drives a signal line includes a first output section for outputting a reference voltage potential to the signal line during a first period and a second output section for outputting one of a first information voltage potential and a second information voltage potential in accordance with an input signal during a second period.

摘要翻译： 驱动信号线的驱动器电路包括：第一输出部，用于在第一时段期间向信号线输出参考电压电位;以及第二输出部，用于输出第一信息电压电位和第二信息电压电位之一 在第二时段期间的输入信号。

公开(公告)号：US5757702A

公开(公告)日：1998-05-26

申请号：US739363

申请日：1996-10-29

申请人： Toru Iwata ,  Hironori Akamatsu ,  Hiroyuki Yamauchi

发明人： Toru Iwata ,  Hironori Akamatsu ,  Hiroyuki Yamauchi

IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C11/419 ,  G11C11/412

摘要： A memory cell includes a first inverter and a second inverter connected with each other through the output node of one of the inverters and the input node of the other inverter, and first and second transistors. Each of the transistors connected with a word line at its gate electrode is interposed between one of a bit line pair and each memory node. This data holding circuit includes an element for increasing a memory cell supply potential for driving the pair of inverters to be higher than a supply potential applied to peripheral circuits, or an element for decreasing a ground voltage for driving the pair of inverters to be lower than a ground voltage applied to the peripheral circuits.

摘要翻译： 存储单元包括通过其中一个反相器的输出节点和另一个反相器的输入节点以及第一和第二晶体管彼此连接的第一反相器和第二反相器。 在其栅电极处与字线连接的晶体管中的每一个插入在位线对和每个存储器节点之一之间。 该数据保持电路包括用于将用于驱动该对反相器的存储单元电源电位增加到高于施加到外围电路的电源电位的元件，或者用于将用于驱动该对反相器的接地电压降低到低于 施加到外围电路的接地电压。