利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

132 条记录 (耗时 0.029 秒)

    Data holding circuit
    4.
    发明授权
    Data holding circuit 失效
    数据保持电路

    公开(公告)号：US5757702A

    公开(公告)日：1998-05-26

    申请号：US739363

    申请日：1996-10-29

    申请人： Toru Iwata ,  Hironori Akamatsu ,  Hiroyuki Yamauchi

    发明人： Toru Iwata ,  Hironori Akamatsu ,  Hiroyuki Yamauchi

    IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C7/00

    CPC分类号： G11C11/419 ,  G11C11/412

    摘要： A memory cell includes a first inverter and a second inverter connected with each other through the output node of one of the inverters and the input node of the other inverter, and first and second transistors. Each of the transistors connected with a word line at its gate electrode is interposed between one of a bit line pair and each memory node. This data holding circuit includes an element for increasing a memory cell supply potential for driving the pair of inverters to be higher than a supply potential applied to peripheral circuits, or an element for decreasing a ground voltage for driving the pair of inverters to be lower than a ground voltage applied to the peripheral circuits.

    摘要翻译： 存储单元包括通过其中一个反相器的输出节点和另一个反相器的输入节点以及第一和第二晶体管彼此连接的第一反相器和第二反相器。 在其栅电极处与字线连接的晶体管中的每一个插入在位线对和每个存储器节点之一之间。 该数据保持电路包括用于将用于驱动该对反相器的存储单元电源电位增加到高于施加到外围电路的电源电位的元件，或者用于将用于驱动该对反相器的接地电压降低到低于 施加到外围电路的接地电压。

    Semiconductor device having a plurality of semiconductor chips connected together by a bus
    5.
    发明授权
    Semiconductor device having a plurality of semiconductor chips connected together by a bus 有权
    具有通过总线连接在一起的多个半导体芯片的半导体装置

    公开(公告)号：US06633607B1

    公开(公告)日：2003-10-14

    申请号：US09249695

    申请日：1999-02-12

    申请人： Hironori Akamatsu ,  Toru Iwata ,  Hiroyuki Yamauchi

    发明人： Hironori Akamatsu ,  Toru Iwata ,  Hiroyuki Yamauchi

    IPC分类号： H03K904

    CPC分类号： H03M9/00 ,  H04L25/49

    摘要： A semiconductor device includes: a transmitting section; and a receiving section, wherein the transmitting section and the receiving section are connected to each other through a bus, the transmitting section includes an encoding section for encoding data including a plurality of bits to produce bit-position information which indicates a position of at least one bit selected from the plurality of bits included in the data, and an output section for outputting the bit-position information onto the bus, and the receiving section includes an input section for receiving the bit-position information from the bus, and a decoding section for decoding the bit-position information to produce the data.

    摘要翻译： 一种半导体器件包括：发送部分; 以及接收部分，其中所述发送部分和所述接收部分通过总线相互连接，所述发送部分包括用于对包括多个比特的数据进行编码的编码部分，以产生指示至少的位置的比特位置信息 从包含在数据中的多个比特中选择一个比特，以及用于将比特位置信息输出到总线上的输出部分，并且接收部分包括用于从总线接收比特位置信息的输入部分和解码 用于解码位位置信息以产生数据。

    Semiconductor memory
    6.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US6009024A

    公开(公告)日：1999-12-28

    申请号：US46880

    申请日：1998-03-24

    申请人： Takashi Hirata ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Keiichi Kusumoto ,  Toru Iwata ,  Satoshi Takahashi ,  Yutaka Terada

    发明人： Takashi Hirata ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Keiichi Kusumoto ,  Toru Iwata ,  Satoshi Takahashi ,  Yutaka Terada

    IPC分类号： G11C7/06 ,  G11C7/00

    CPC分类号： G11C7/06

    摘要： A semiconductor memory of the present invention includes: a plurality of memory cells; a pair of local bit lines connected to the plurality of memory cells; a local sense amplifier for amplifying a potential difference between the pair of local bit lines; a pair of global bit lines electrically connected to the pair of local bit lines through a switch; and a global sense amplifier for amplifying a potential difference between the pair of global bit lines, wherein the local sense amplifier includes a plurality of transistors, each of the plurality of transistors included in the local sense amplifier is a transistor of a first conductivity type, and the global sense amplifier includes a transistor of a second conductivity type different from the first conductivity type.

    摘要翻译： 本发明的半导体存储器包括：多个存储单元; 连接到所述多个存储器单元的一对局部位线; 本地读出放大器，用于放大一对局部位线之间的电位差; 一对全局位线通过开关电连接到该对局部位线; 以及用于放大所述一对全局位线之间的电位差的全局读出放大器，其中所述局部读出放大器包括多个晶体管，所述局部读出放大器中包括的所述多个晶体管中的每一个是第一导电类型的晶体管， 并且全球感测放大器包括不同于第一导电类型的第二导电类型的晶体管。

    Memory access buffer and reordering apparatus using priorities
    8.
    发明授权
    Memory access buffer and reordering apparatus using priorities 失效
    使用优先级的存储器访问缓冲器和重新排序装置

    公开(公告)号：US6145065A

    公开(公告)日：2000-11-07

    申请号：US67899

    申请日：1998-04-29

    申请人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Keiichi Kusumoto ,  Toru Iwata ,  Yutaka Terada ,  Takashi Hirata

    发明人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Keiichi Kusumoto ,  Toru Iwata ,  Yutaka Terada ,  Takashi Hirata

    IPC分类号： G06F13/16 ,  G06F12/02

    CPC分类号： G06F13/1631

    摘要： A current problem is that when a DRAM is to be accessed through a data bus, the DRAM is accessed independently of a bank, a row address, etc., and therefore, is inefficient. To solve this problem, an address bus and a data bus are connected to a main memory part independently of each other, a temporary memory part for holding a plurality of addresses in advance is disposed on the address bus side and holds addresses for every access to the main memory part regardless of transfer of data, thereby pipelining address inputting cycles. Further, for the purpose of an effective operation of the main memory part, using the addresses which are held, the addresses are rearranged in such a manner that addresses with the same row addresses become continuous to each other, or when there are not addresses with the same row addresses, addresses different banks from each other become continuous to each other, and the memory is thereafter accessed. This reduces the number of precharges, shortens a standby period which is necessary for a precharge, and realizes accessing while reducing a wasteful use of time.

    摘要翻译： 目前的问题在于，当通过数据总线访问DRAM时，独立于存储体，行地址等访问DRAM，因此是低效的。 为了解决这个问题，地址总线和数据总线彼此独立地连接到主存储器部分，预先存储多个地址的临时存储器部分设置在地址总线侧，并且保存地址以进行每次访问 主存储部分不管数据传输，从而流水线地址输入周期。 此外，为了主存储器部分的有效操作，使用所保存的地址，地址被重新排列，使得具有相同行地址的地址彼此连续，或者当没有地址与 相同的行地址，彼此不同的存储体彼此变得连续，并且此后访问存储器。 这减少了预充电次数，缩短了预充电所需的待机时间，并实现了访问，同时减少了浪费时间的使用。

    Network unit with power saving mode inhibit based on interconnection relationship to neighboring nodes which is stored on the unit
    9.
    发明授权
    Network unit with power saving mode inhibit based on interconnection relationship to neighboring nodes which is stored on the unit 有权
    具有省电模式的网络单元基于与存储在单元上的相邻节点的互连关系而禁止

    公开(公告)号：US06604201B1

    公开(公告)日：2003-08-05

    申请号：US09428277

    申请日：1999-10-27

    申请人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Tadahiro Yoshida ,  Yutaka Terada ,  Yukio Arima ,  Takashi Hirata ,  Yoshihide Komatsu

    发明人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Tadahiro Yoshida ,  Yutaka Terada ,  Yukio Arima ,  Takashi Hirata ,  Yoshihide Komatsu

    IPC分类号： G06F132

    CPC分类号： H04L12/12 ,  Y02D50/20 ,  Y02D50/40

    摘要： A power-saving network unit, which is connected to a network made up of a plurality of power-saving network units, includes: network monitoring means; network information memory; power-saving mode setting means; peripheral I/O interface; and digital processor. The network monitoring means monitors a topology of the network, or the interconnection relationship among the power-saving network units. Every time the network has been modified, the network monitoring means stores the modified network topology on the network information memory. The power-saving mode setting means receives the network information stored on the network information memory. If the power-saving network unit is a master or relay node in the network, then the power-saving mode setting means locks the peripheral I/O interface and digital processor of the power-saving network unit to the normal operation mode and prohibits these sections from entering the power-saving mode.

    摘要翻译： 连接到由多个省电网络单元组成的网络的节电网单元包括：网络监控装置; 网络信息记忆; 省电模式设定手段; 外设I / O接口; 和数字处理器。 网络监控装置监控网络的拓扑结构，或节能网络单元之间的互连关系。 每当网络被修改时，网络监控装置将修改的网络拓扑存储在网络信息存储器上。 省电模式设置装置接收存储在网络信息存储器上的网络信息。 如果省电网络单元是网络中的主节点或中继节点，则省电模式设置装置将节电网络单元的外围I / O接口和数字处理器锁定到正常操作模式，并禁止这些 部分进入省电模式。