公开(公告)号：US08296621B2

公开(公告)日：2012-10-23

申请号：US12593514

申请日：2007-04-04

Applicant: Mathieu Villion

Inventor： Mathieu Villion

IPC: H03M13/00

CPC classification number: H03M13/03 ,  H04L1/0052 ,  H04N21/4382 ,  H04N21/64315

Abstract: An integrated circuit comprises forward error correction (FEC) decoder logic being coupled to memory and arranged to receive data, comprising application data, from a host application process. The FEC decoder logic performs error detection upon the received data. Logic is further arranged to transmit error free application data back to the host application process prior to performing error correction; and store in memory only application data in which errors are detected.

Abstract translation: 集成电路包括耦合到存储器的前向纠错（FEC）解码器逻辑，并且被布置成从主机应用进程接收包括应用数据的数据。 FEC解码器逻辑对接收到的数据执行错误检测。 逻辑还被布置为在执行纠错之前将无错误的应用数据发送回主机应用进程; 并在存储器中仅存储检测到错误的应用程序数据。

公开(公告)号：US20100316117A1

公开(公告)日：2010-12-16

申请号：US12866244

申请日：2008-02-11

Applicant: Mathieu Villion ,  Laurence Poirier-Clarac ,  Pierre Tardy

Inventor： Mathieu Villion ,  Laurence Poirier-Clarac ,  Pierre Tardy

IPC: H04N11/04

CPC classification number: H04L1/0054 ,  H03M13/2936 ,  H03M13/2948 ,  H03M13/2957 ,  H03M13/63 ,  H04L1/0038 ,  H04L1/0065 ,  H04L1/007 ,  H04L1/0072 ,  H04L1/0082

Abstract: Decoding logic is arranged to receive an encoded data signal. The decoding logic comprises a convolutional decoder arranged to perform convolutional decoding on the encoded data signal, to produce a decoded data signal. The decoding logic comprises header bit prediction logic arranged to predict a value for at least one header bit within the decoded data signal, and to provide the predicted value for the at least one header bit to the convolutional decoder to be applied during convolutional decoding.

Abstract translation: 解码逻辑被布置成接收编码的数据信号。 解码逻辑包括卷积解码器，被布置为对编码的数据信号执行卷积解码，以产生解码的数据信号。 解码逻辑包括头部比特预测逻辑，其被布置为预测解码数据信号内的至少一个头部比特的值，并且为卷积解码期间要应用的卷积解码器提供至少一个头部比特的预测值。

公开(公告)号：US06983162B2

公开(公告)日：2006-01-03

申请号：US10489230

申请日：2002-05-27

Applicant: Pradeep Garani ,  Mathieu Villion ,  Michael Kotzin ,  Ray Owen

Inventor： Pradeep Garani ,  Mathieu Villion ,  Michael Kotzin ,  Ray Owen

IPC: H04B7/00 ,  H04B7/15 ,  H04B7/185 ,  H04B15/00 ,  H04Q7/20

CPC classification number: H04W4/08 ,  H04B7/2606 ,  H04W8/005 ,  H04W88/04

Abstract: A method of enhancing a communication capability of a communication unit (112), operating in a communication system (100) that facilitates communication to and/or from a plurality of communication units. The method includes the step of operably coupling a first communication unit (112) to one or more neighboring communication units (114, 116) such that said communication unit is able to utilize at least one operational capability of one or more of its neighboring communication units to enhance communication to and/or from said first communication unit.

Abstract translation: 一种增强通信单元（112）的通信能力的方法，该通信单元在促进与多个通信单元的通信和/或从多个通信单元的通信系统（100）中操作。 该方法包括将第一通信单元（112）可操作地耦合到一个或多个相邻通信单元（114,116）的步骤，使得所述通信单元能够利用其相邻通信单元中的一个或多个的至少一个操作能力 以增强与所述第一通信单元的通信和/或从所述第一通信单元的通信。