摘要:
A power management scheme for a wireless communications device processor substantially implemented on a single CMOS integrated circuit is described. By incorporating controls for sleep and wake-up mode transitions in the processor's control logic, improved power savings with reduced latency is provided, obviating the need for hardware-focused solutions with elaborate signaling mechanisms. A fully integrated power management with staged wake-up operations controlled by the MAC solution consumes less power than the conventional wireless LAN solutions in standby mode.
摘要:
A power management scheme for a wireless communications device processor substantially implemented on a single CMOS integrated circuit is described. By incorporating controls for sleep and wake-up mode transitions in the processor's control logic, improved power savings with reduced latency is provided, obviating the need for hardware-focused solutions with elaborate signaling mechanisms. A fully integrated power management with staged wake-up operations controlled by the MAC solution consumes less power than the conventional wireless LAN solutions in standby mode.
摘要:
A meat packaging apparatus includes a tray containing a modified atmosphere and meat product, a film sealed to the tray and including an opening, and a two-piece label attached to the film and covering the opening. The two-piece label including a first layer removably attached to a second layer, which is attached to the film. The second layer is made of a highly oxygen permeable material to allow oxygen to enter the tray when the top layer is removed.
摘要:
A symbolic language data processing system comprises a sequencer unit, a data path unit, a memory control unit, a front-end processor, an I/O and a main memory connected on a common Lbus to which other peripherals and data units can be connected for intercommunication. The system architecture includes a novel bus network, a synergistic combination of the Lbus, microtasking, centralized error correction circuitry and a synchronous pipelined memory including processor mediated direct memory access, stack cache windows with two segment addressing, a page hash table and page hash table cache, garbage collection and pointer control, a close connection of the macrocode and microcode which enables one to take interrupts in and out of the macrocode instruction sequences, parallel data type checking with tagged architecture, procedure call and microcode support, a generic bus and a unique instruction set to support symbolic language processing.
摘要:
A Wireless Local Area Network (WLAN) system based upon peer-to-peer communications. A wireless terminal for peer-to-peer communications acts either as a WLAN master or as a WLAN slave. When the wireless terminal acts a master, the wireless terminal undertakes mastering duties that include transmitting a beacon interval in the frame cycle. When the wireless terminal is not tethered to a power source, mastering duties alternate according to a round-robin WLAN mastering cycle, wherein the wireless terminal acts the WLAN master during at least one frame cycle and acts the WLAN slave during other frame cycles to conserve an untethered power source of the wireless terminal.
摘要:
A Wireless Local Area Network (WLAN) system based upon peer-to-peer communications. A wireless terminal for peer-to-peer communications acts either as a WLAN master or as a WLAN slave. When the wireless terminal acts a master, the wireless terminal undertakes mastering duties that include transmitting a beacon interval in the frame cycle. When the wireless terminal is not tethered to a power source, mastering duties alternate according to a round-robin WLAN mastering cycle, wherein the wireless terminal acts the WLAN master during at least one frame cycle and acts the WLAN slave during other frame cycles to conserve an untethered power source of the wireless terminal.
摘要:
A power management scheme for a wireless communications device processor substantially implemented on a single CMOS integrated circuit is described. By incorporating controls for sleep and wake-up mode transitions in the processor's control logic, improved power savings with reduced latency is provided, obviating the need for hardware-focused solutions with elaborate signaling mechanisms. A fully integrated power management with staged wake-up operations controlled by the MAC solution consumes less power than the conventional wireless LAN solutions in standby mode.
摘要:
A method of scheduling program instructions for execution in a computer processor comprises fetching and holding instructions from an instruction memory and executing the fetched instructions out of program order. When load/store order violations are detected, the effects of the load operation and its dependent instructions are erased and they are re-executed. The load is associated with all stores on whose data the load depends. This collection of stores is called a store set. On a subsequent issuance of the load, its execution is delayed until any store in the load's store set has issued. Two loads may share a store set, and separate store sets are merged when a load from one store set is found to depend on a store from another store set. A preferred embodiment employs two tables. The first is a store set ID table (SSIT) which is indexed by part of, or a hash of, an instruction PC. Entries in the SSIT provide a store set ID which is used to index into the second table, which for each store set, contains a pointer to the last fetched, unexecuted store instruction.
摘要:
A symbolic language data processing system comprises a sequencer unit, a data path unit, a memory control unit, a front-end processor, an I/O and a main memory connected on a common Lbus to which other peripherals and data units can be connected for intercommunication. The system architecture includes a novel bus network, a synergistic combination of the Lbus, microtasking, centralized error correction circuitry and a synchronous pipelined memory including processor mediated direct memory access, stack cache windows with two segment addressing, a page hash table and page hash table cache, garbage collection and pointer control a close connection of the macrocode and microcode which enables one to take interrupts in and out of the macrocode instruction sequences, parallel data type checking with tagged architecture, procedure call and microcode support, a generic bus and a unique insruction set to support symbolic language processing.
摘要:
A power management scheme for a wireless communications device processor substantially implemented on a single CMOS integrated circuit is described. By incorporating controls for sleep and wake-up mode transitions in the processor's control logic, improved power savings with reduced latency is provided, obviating the need for hardware-focused solutions with elaborate signaling mechanisms. A fully integrated power management with staged wake-up operations controlled by the MAC solution consumes less power than the conventional wireless LAN solutions in standby mode.