摘要:
A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.
摘要:
A fabricated layered capacitor having three layers is provided. The first bottom layer comprises a first bottom plate portion, the second middle layer comprises a first top plate portion, and the third top layer comprises a second bottom plate portion of the layered capacitor. A set of vias connects the first and second bottom plate portions. The top plate portion may extend past the bottom plate portions. The layered capacitor may have a different number of layers (e.g., five layers). The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more layered capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.
摘要:
A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.
摘要:
A line driver fabricated from CMOS devices that provides a substantially constant output impedance over a significant range of a time-varying input voltage includes a time-varying current source, a pair of CMOS output loads, and a pair of biasing circuits. Each CMOS output load includes a NMOS transistor and a PMOS transistor connected in parallel and each biased into a linear range of operation. In response to a time-varying input voltage, the time-varying current source draws current from the pair of CMOS output loads in a manner that operates each CMOS output load to collectively establish a time-varying output voltage component at an associated output terminal.
摘要:
The invention relates to a clock signal frequency multiplier circuit. The circuit multiplies the speed of a clock signal of an integrated circuit (IC) by a factor N to generate a times-N clock signal. The circuit first receives a clock signal. Next, the circuit replicates the clock signal into a plurality of N component signals. Each Jth component signal is delayed from the (J-1)th component signal by 1/N cycles, where J equals 1 to N. The (J=1)th component signal is the clock signal. The N component signals are referred to as phase-shifted components. Finally, the circuit logically combines the phase-shifted components into a times-N clock signal.