Fabricated layered capacitor for a digital-to-analog converter
    12.
    发明授权
    Fabricated layered capacitor for a digital-to-analog converter 失效
    用于数模转换器的制造分层电容器

    公开(公告)号:US07446365B1

    公开(公告)日:2008-11-04

    申请号:US11371257

    申请日:2006-03-07

    IPC分类号: H01L27/108

    摘要: A fabricated layered capacitor having three layers is provided. The first bottom layer comprises a first bottom plate portion, the second middle layer comprises a first top plate portion, and the third top layer comprises a second bottom plate portion of the layered capacitor. A set of vias connects the first and second bottom plate portions. The top plate portion may extend past the bottom plate portions. The layered capacitor may have a different number of layers (e.g., five layers). The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more layered capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.

    摘要翻译: 提供了具有三层的制造的层状电容器。 第一底层包括第一底板部分,第二中间层包括第一顶板部分,第三顶层包括层状电容器的第二底板部分。 一组通孔连接第一和第二底板部分。 顶板部分可延伸穿过底板部分。 分层电容器可以具有不同数量的层(例如,五层)。 这些层可以包括使用半导体制造方法制造的金属层。 还提供了一种具有两个或更多个分层电容器的电容器阵列,其中连接器连接电容器的所有顶板部分。 电容器阵列可用于电容式DAC,电容器根据DAC的结构进行连接。 电容式DAC可用于SAR ADC。

    Variable frequency clock generator for synchronizing data rates between clock domains in radio frequency wireless communication systems
    13.
    发明授权
    Variable frequency clock generator for synchronizing data rates between clock domains in radio frequency wireless communication systems 有权
    可变频时钟发生器,用于在射频无线通信系统中的时钟域之间同步数据速率

    公开(公告)号:US07389095B1

    公开(公告)日:2008-06-17

    申请号:US11132978

    申请日:2005-05-18

    IPC分类号: H04B1/06

    CPC分类号: H04B15/02 H04B2215/067

    摘要: A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.

    摘要翻译: 公开了一种系统,方法和系统,用于使用可变频率时钟发生器在可变时钟域中的时间间隔上同步平均数据速率,使其等于固定时钟域中的固定数据速率,同时减少电磁干扰,其中 其他事情。 在各种实施例中,将数据速率设置为彼此相等最小化用于在时钟域之间转换数据信号的存储。 在一个实施例中,可变频率时钟发生器包括被配置为形成可变频率时钟的相位调制器。 此外,可变时钟发生器被配置为在离散频率的范围内保持特定时间段的平均频率。 相位偏移控制器设置在固定时钟域中的固定数据速率与可变时钟域中的平均数据速率之间基本上没有偏移的平均时钟。

    CMOS controlled-impedance transmission line driver
    14.
    发明授权
    CMOS controlled-impedance transmission line driver 有权
    CMOS控制阻抗传输线驱动器

    公开(公告)号:US06909310B2

    公开(公告)日:2005-06-21

    申请号:US10354281

    申请日:2003-01-30

    IPC分类号: H03K17/041 H04L25/02 H03B1/00

    摘要: A line driver fabricated from CMOS devices that provides a substantially constant output impedance over a significant range of a time-varying input voltage includes a time-varying current source, a pair of CMOS output loads, and a pair of biasing circuits. Each CMOS output load includes a NMOS transistor and a PMOS transistor connected in parallel and each biased into a linear range of operation. In response to a time-varying input voltage, the time-varying current source draws current from the pair of CMOS output loads in a manner that operates each CMOS output load to collectively establish a time-varying output voltage component at an associated output terminal.

    摘要翻译: 由CMOS器件制造的线路驱动器,其在时变输入电压的有效范围内提供基本上恒定的输出阻抗,包括时变电流源,一对CMOS输出负载和一对偏置电路。 每个CMOS输出负载包括并联连接的NMOS晶体管和PMOS晶体管,并且各自被偏置成线性的操作范围。 响应于时变输入电压,随时间变化的电流源以操作每个CMOS输出负载的方式从一对CMOS输出负载中抽取电流,以共同建立相关输出端子处的时变输出电压分量。

    Clock signal frequency multiplier
    15.
    发明授权
    Clock signal frequency multiplier 失效
    时钟信号倍频器

    公开(公告)号:US5821785A

    公开(公告)日:1998-10-13

    申请号:US691765

    申请日:1996-08-02

    摘要: The invention relates to a clock signal frequency multiplier circuit. The circuit multiplies the speed of a clock signal of an integrated circuit (IC) by a factor N to generate a times-N clock signal. The circuit first receives a clock signal. Next, the circuit replicates the clock signal into a plurality of N component signals. Each Jth component signal is delayed from the (J-1)th component signal by 1/N cycles, where J equals 1 to N. The (J=1)th component signal is the clock signal. The N component signals are referred to as phase-shifted components. Finally, the circuit logically combines the phase-shifted components into a times-N clock signal.

    摘要翻译: 本发明涉及时钟信号倍频电路。 该电路将集成电路(IC)的时钟信号的速度乘以因子N以产生时间N时钟信号。 电路首先接收时钟信号。 接下来,电路将时钟信号复制成多个N个分量信号。 每个第j个分量信号从第(J-1)个分量信号延迟1 / N个周期,其中J等于1到N.第(J = 1)分量信号是时钟信号。 N分量信号被称为相移分量。 最后,电路逻辑地将相移分量组合成N次时钟信号。