公开(公告)号：US20090133522A1

公开(公告)日：2009-05-28

申请号：US11945950

申请日：2007-11-27

Applicant: Meng-Lin Yu ,  Hung-Yu Su ,  Sam Huang

Inventor： Meng-Lin Yu ,  Hung-Yu Su ,  Sam Huang

IPC: F16H3/08

CPC classification number: B62M7/12 ,  F16H57/02 ,  F16H57/031 ,  F16H2057/02013 ,  Y10T74/19219 ,  Y10T74/2186

Abstract: A vehicle transmission is adapted to transmit a power output from an engine unit to a wheel. The vehicle transmission includes a driving unit and a speed-changing unit. The driving unit includes a main box, a first driving mechanism disposed within the main box and adapted to be driven by the engine unit, and an output shaft driven by the first driving mechanism. The speed-changing unit includes an auxiliary box connected removably to the main box, a second driving mechanism disposed within the auxiliary box and driven by the output shaft, and an axle parallel to the output shaft and driven by the second driving mechanism. The axle is connected fixedly to the wheel, and extends into the auxiliary box.

Abstract translation: 车辆变速器适于将从发动机单元输出的功率传递到车轮。 车辆变速器包括驱动单元和变速单元。 驱动单元包括主箱，设置在主箱内并适于由发动机单元驱动的第一驱动机构和由第一驱动机构驱动的输出轴。 变速单元包括可拆卸地连接到主箱的辅助箱，设置在辅助箱内并由输出轴驱动的第二驱动机构，以及平行于输出轴并由第二驱动机构驱动的轴。 轴固定在车轮上，并延伸到辅助箱中。

公开(公告)号：US09100228B2

公开(公告)日：2015-08-04

申请号：US12907435

申请日：2010-10-19

Applicant: Samer Hijazi ,  Kameran Azadet ,  Meng-Lin Yu ,  Joseph Othmer ,  Ramon Sanchez Perez

Inventor： Samer Hijazi ,  Kameran Azadet ,  Meng-Lin Yu ,  Joseph Othmer ,  Ramon Sanchez Perez

IPC: H04B17/00 ,  H04L25/02

CPC classification number: H04L25/0232 ,  H04L25/0212 ,  H04L25/0226

Abstract: A method and system for canonical channel estimation in the Long Term Evolution uplink where a multi-frequency signal is generated and then converted to frequency spectrum which is then convolved in the frequency domain with a truncated window function to obtain a time domain channel impulse response. The time domain channel impulse response can be then transformed to a frequency domain to produce a down sampled user channel response, which can be then linearly interpolated to provide a channel estimate for a plurality of subcarriers. Such an approach achieves channel estimation within Long Term Evolution at only canonical locations to reduce complexity without loss in channel entropy.

Abstract translation: 一种用于在长期演进上行链路中进行规范信道估计的方法和系统，其中生成多频信号，然后将其转换为频谱，然后将频谱卷积在具有截断窗函数的频域中以获得时域信道脉冲响应。 然后可以将时域信道脉冲响应变换到频域以产生下采样的用户信道响应，然后可以对其进行线性内插以提供多个子载波的信道估计。 这种方法在长期演进中仅在规范位置实现信道估计，以减少复杂度而不损失信道熵。

公开(公告)号：US08842665B2

公开(公告)日：2014-09-23

申请号：US13587983

申请日：2012-08-17

Applicant: Chengzhou Li ,  Meng-Lin Yu

Inventor： Chengzhou Li ,  Meng-Lin Yu

IPC: H04Q11/00 ,  H04L12/00 ,  H04J3/04 ,  H04B1/06

CPC classification number: G06F17/145 ,  H04B1/707

Abstract: A method of applying an order N fast Hadamard transform (FHT) of a vector U using a mixed radix FHT in a receiver of a communication system, the N a positive integer, when receiving signals from a transmitter over a channel and generating the vector U. The method includes, in an FHT module of a decoder in the receiver, planning n stages of the mixed radix FHT, where the n is a positive integer, each stage defined by corresponding logic, decomposing the order N FHT into n low order FHTs, such that N=KnKn−1 . . . K1 and U=UKnKn−1 . . . K1, where the K is a positive integer, calculating, via the corresponding logic, each low order FHT at each stage, wherein input vectors of a subsequent stage are calculated in a proceeding stage, and reconstructing, by the decoder, calculated results of the each low order FHT to form an output vector output the decoder.

Abstract translation: 一种在通信系统的接收机中使用混合基数FHT应用向量U的N阶快速Hadamard变换（FHT）的方法，当在通道上从发送器接收信号并产生向量U时，N为正整数 该方法包括在接收机中的解码器的FHT模块中，规划混合基数FHT的n个阶段，其中n是正整数，每个阶段由对应的逻辑定义，将阶N FHT分解为n个低阶FHT ，使得N = KnKn-1。 。 。 K1和U = UKnKn-1。 。 。 K1，其中K是正整数，通过相应的逻辑，在每个阶段计算每个低阶FHT，其中在后续阶段中计算后级的输入向量，并且由解码器重建计算结果 每个低阶FHT形成输出向量输出解码器。

公开(公告)号：US20130195007A1

公开(公告)日：2013-08-01

申请号：US13566146

申请日：2012-08-03

Applicant: Ivan Leonidovich Mazurenko ,  Alexander Alexandrovich Petyushko ,  Meng-Lin Yu ,  Jian-Guo Chen

Inventor： Ivan Leonidovich Mazurenko ,  Alexander Alexandrovich Petyushko ,  Meng-Lin Yu ,  Jian-Guo Chen

IPC: H04W4/00

CPC classification number: H04B1/70755 ,  H04L7/042

Abstract: In one embodiment, the present invention is a method for performing incremental preamble detection in a wireless communication network. The method processes non-overlapping chunks of incoming antenna data, where each chunk is smaller than the preamble length, to detect the signature of the transmitted preamble. For each chunk processed, chips of the chunk are correlated with possible signatures employed by the wireless network to update a set of correlation profiles, each profile comprising a plurality of profile values. Further, an intermediate detection is performed by comparing the updated profile values to an intermediate threshold that is also updated for each chunk. Upon receiving the final chunk, the correlation profiles are updated, and a final preamble detection is made by comparing the updated profile values to a final threshold. Detections are performed on an incremental basis to meet latency requirements of the wireless network.

Abstract translation: 在一个实施例中，本发明是一种用于在无线通信网络中执行增量前导码检测的方法。 该方法处理输入天线数据的不重叠块，其中每个块小于前导码长度，以检测所发送的前导码的签名。 对于处理的每个块，块的码片与由无线网络使用的可能的签名相关联，以更新一组相关轮廓，每个轮廓包括多个轮廓值。 此外，通过将更新的简档值与也为每个块更新的中间阈值进行比较来执行中间检测。 在接收到最后的块之后，更新相关轮廓，并且通过将更新的简档值与最终的阈值进​​行比较来进行最终的前导码检测。 检测是按增量执行的，以满足无线网络的延迟要求。

公开(公告)号：US20120030450A1

公开(公告)日：2012-02-02

申请号：US12845118

申请日：2010-07-28

Applicant: Meng-Lin Yu

Inventor： Meng-Lin Yu

IPC: G06F9/38

CPC classification number: G06F9/30007 ,  G06F7/5443 ,  G06F17/10

Abstract: A method and system for parallel computation of a linear sequential circuit (LSC) based on a state transition matrix is disclosed herein. A multistep state transition matrix and a multistep output generation matrix can be pre-computed and stored in association with the linear sequential circuit. The multiple state transitions and the multiple output bits can be computed by multiplying the current input-state vector with a multistep next state transition matrix and a multistep output generation matrix, respectively. Multiple state transitions and multiple output bits can be generated in parallel in a single clock cycle based on the pre-computed state transition matrix and the output generation matrix utilizing a dot product in order to improve computational speed. Such a simple augmentation provides a flexible and inexpensive solution for high speedup linear sequential circuit computation with respect to a processor.

Abstract translation: 本文公开了一种用于基于状态转移矩阵的线性顺序电路（LSC）的并行计算的方法和系统。 可以与线性顺序电路相关联地预先计算和存储多步状态转移矩阵和多步骤输出生成矩阵。 可以通过将当前输入状态向量与多步下一状态转移矩阵和多步输出生成矩阵相乘来计算多状态转换和多输出位。 基于预先计算的状态转移矩阵和利用点积的输出生成矩阵，可以在单个时钟周期中并行地生成多个状态转换和多个输出位，以便提高计算速度。 这样一个简单的扩充为处理器的高速线性时序电路计算提供了灵活和便宜的解决方案。

公开(公告)号：US07254771B1

公开(公告)日：2007-08-07

申请号：US09577177

申请日：2000-05-23

Applicant: Leilei Song ,  Meng-Lin Yu

Inventor： Leilei Song ,  Meng-Lin Yu

IPC: H03M13/00

CPC classification number: H03M13/154 ,  H03M13/2954 ,  H03M13/6561

Abstract: A method of decoding interleaved Reed-Solomon codes to achieve an improved performance for burst errors is described. The method takes advantage of both interleaving and erasure decoding to increase the error correcting capability of a system without necessarily depending on channel reliability information. The observed correlation of burst errors in interleaved systems is advantageously used to achieve an improved error-correcting system, wherein a first code word is decoded, and the error locations in the first codeword are used to determine erasures for the remaining code words in the same interleaving block, and finally, decoding the remaining code words in parallel.

Abstract translation: 描述了对交错的里德 - 所罗门码进行解码以实现突发错误的改进性能的方法。 该方法利用交织和擦除解码来增加系统的纠错能力，而不必依赖于信道可靠性信息。 观察到交织系统中突发错误的相关性有利地用于实现改进的纠错系统，其中第一码字被解码，并且第一码字中的错误位置被用于确定相同的剩余码字的擦除 交织块，最后并行解码剩余码字。

公开(公告)号：US06940924B1

公开(公告)日：2005-09-06

申请号：US09639259

申请日：2000-08-15

Applicant: Helen H. Kim ,  Meng-Lin Yu

Inventor： Helen H. Kim ,  Meng-Lin Yu

IPC: H03H7/40 ,  H04L1/00 ,  H04L25/03 ,  H04L27/06

CPC classification number: H04L25/03057 ,  H04L25/03171

Abstract: A receiver for a received signal having two or more different data levels comprises two or more channel estimators, (at least) one channel estimator for each different data level, where each channel estimator preferably implements an adaptive 2nd order or higher model of the transmission channel over which the received signals was transmitted to generate an estimated signal for one of the different data levels. The receiver also has a comparator that compares the current received signal to the estimated signals generated by the different channel estimators to select an output data value for the current received signal. The adaptive model of the transmission channel has coefficients that are dynamically controlled based on an error signal generated by the comparator. Each channel estimator relies on an output signal generated by an adaptive equalizer. In preferred shared-component implementations, each adaptive equalizer is shared by two or more different channel estimators, and, in one possible preferred shared-component implementation, all of the different channel estimators share a single adaptive equalizer.

Abstract translation: 用于具有两个或多个不同数据电平的接收信号的接收机包括用于每个不同数据电平的两个或更多个信道估计器（至少）一个信道估计器，其中每个信道估计器优选地实现自适应二进制/ 发送信号的传输信道的订单或更高模型，以生成用于不同数据电平之一的估计信号。 接收机还具有比较器，其将当前接收信号与由不同信道估计器生成的估计信号进行比较，以选择当前接收信号的输出数据值。 传输信道的自适应模型具有基于由比较器产生的误差信号而动态控制的系数。 每个信道估计器依赖于由自适应均衡器产生的输出信号。 在优选的共享分量实现中，每个自适应均衡器由两个或更多个不同的信道估计器共享，并且在一个可能的优选共享分量实现中，所有不同的信道估计器共享单个自适应均衡器。

公开(公告)号：US6028993A

公开(公告)日：2000-02-22

申请号：US781882

申请日：1997-01-10

Applicant: Meng-Lin Yu ,  P. A. Subrahmanyam

Inventor： Meng-Lin Yu ,  P. A. Subrahmanyam

IPC: G06F17/50

CPC classification number: G06F17/5027

Abstract: A logic circuit is simulated for mapping and emulation on a field programmable gate array-based platform by mapping one or more of the circuit delays onto delay elements in the FPGA-based platform. The operations of the delay elements are controlled by one or more simulations clocks that are different from any user-specified clocks.

Abstract translation: 通过将一个或多个电路延迟映射到基于FPGA的平台中的延迟元件上，在基于现场可编程门阵列的平台上仿真用于映射和仿真的逻辑电路。 延迟元件的操作由一个或多个与任何用户指定的时钟不同的仿真时钟来控制。

公开(公告)号：US08719323B2

公开(公告)日：2014-05-06

申请号：US12910065

申请日：2010-10-22

Applicant: Meng-Lin Yu

Inventor： Meng-Lin Yu

IPC: G06F7/00

CPC classification number: H04L25/0232 ,  H04L25/0212 ,  H04L25/0226

Abstract: A method for efficient state transition matrix based LFSR computations are disclosed. A polynomial associated with a linear feedback shift register is defined. This polynomial is used to generate a single step state transition matrix. The single step state transition matrix is then modified into a more general k-step state transition matrix. The resultant combined matrix is reduced in size and can be multiplied by a state input vector, ultimately producing a plurality of next state-input vectors thereby providing improved efficiency in computing a LFSR.

Abstract translation: 公开了一种基于有效状态转移矩阵的LFSR计算的方法。 定义与线性反馈移位寄存器相关联的多项式。 该多项式用于生成单步状态转移矩阵。 然后将单步状态转换矩阵修改为更通用的k阶状态转换矩阵。 所得到的组合矩阵的尺寸减小并且可以乘以状态输入向量，最终产生多个下一个状态输入向量，从而提供计算LFSR的提高的效率。

公开(公告)号：US08504603B2

公开(公告)日：2013-08-06

申请号：US12845118

申请日：2010-07-28

Applicant: Meng-Lin Yu

Inventor： Meng-Lin Yu

IPC: G06F7/00

CPC classification number: G06F9/30007 ,  G06F7/5443 ,  G06F17/10

Abstract: A method and system for parallel computation of a linear sequential circuit (LSC) based on a state transition matrix is disclosed herein. A multistep state transition matrix and a multistep output generation matrix can be pre-computed and stored in association with the linear sequential circuit. The multiple state transitions and the multiple output bits can be computed by multiplying the current input-state vector with a multistep next state transition matrix and a multistep output generation matrix, respectively. Multiple state transitions and multiple output bits can be generated in parallel in a single clock cycle based on the pre-computed state transition matrix and the output generation matrix utilizing a dot product in order to improve computational speed. Such a simple augmentation provides a flexible and inexpensive solution for high speedup linear sequential circuit computation with respect to a processor.

Abstract translation: 本文公开了一种用于基于状态转移矩阵的线性顺序电路（LSC）的并行计算的方法和系统。 可以与线性顺序电路相关联地预先计算和存储多步状态转移矩阵和多步骤输出生成矩阵。 可以通过将当前输入状态向量与多步下一状态转移矩阵和多步输出生成矩阵相乘来计算多状态转换和多输出位。 基于预先计算的状态转移矩阵和利用点积的输出生成矩阵，可以在单个时钟周期中并行地生成多个状态转换和多个输出位，以便提高计算速度。 这样一个简单的扩充为处理器的高速线性时序电路计算提供了灵活和便宜的解决方案。