公开(公告)号：US20070210454A1

公开(公告)日：2007-09-13

申请号：US11748472

申请日：2007-05-14

Applicant: Pei-Yu Chou ,  Chun-Jen Huang

Inventor： Pei-Yu Chou ,  Chun-Jen Huang

IPC: H01L23/52

CPC classification number: H01L21/76844 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76829

Abstract: A process and structure for a metal interconnect comprises providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.

Abstract translation: 用于金属互连的工艺和结构包括：使用第一图案化硬掩模提供具有第一电导体，形成第一介电层和第一图案化硬掩模的基板，以形成第一开口和第二导电体，形成第二导体 电介质层和第二图案化硬掩模，使用第二图案化硬掩模作为蚀刻掩模，并使用第一图案化硬掩模作为蚀刻停止层以形成第二开口和第三导电体。

公开(公告)号：US08080877B2

公开(公告)日：2011-12-20

申请号：US12821136

申请日：2010-06-23

Applicant: Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

Inventor： Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76811

Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.

Abstract translation: 公开了一种双镶嵌工艺。 提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。 介电层沉积在盖层上。 氧化硅层沉积在电介质层上。 在氧化硅层上形成金属硬掩模。 将沟槽开口蚀刻到金属硬掩模中。 部分通孔特征被蚀刻到沟槽开口内的电介质层中。 沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。 执行衬垫去除步骤以通过使用CF4 / NF3等离子体从双镶嵌开口选择性地去除暴露的盖层。

公开(公告)号：US20110248747A1

公开(公告)日：2011-10-13

申请号：US13081472

申请日：2011-04-06

Applicant: Chun-Jen Huang

Inventor： Chun-Jen Huang

IPC: H02M1/00

CPC classification number: G05F3/30

Abstract: General speaking, a resistor of high resistivity has a negative-temperature-coefficient and a resistor of low resistivity has a positive-temperature-coefficient. Utilizing this characteristic, an appropriate proportion between the above resistors can be found to make a combined resistor with an approximate zero-temperature-coefficient. The combined resistor can be used to design a circuit for generating voltage and current with approximate zero-temperature-coefficients.

Abstract translation: 一般来说，高电阻率的电阻器具有负温度系数，低电阻率的电阻器具有正温度系数。 利用该特性，可以发现上述电阻器之间的适当比例使得具有近似零温度系数的组合电阻器。 组合电阻器可用于设计用于产生具有近似零温度系数的电压和电流的电路。

公开(公告)号：US20100258941A1

公开(公告)日：2010-10-14

申请号：US12821136

申请日：2010-06-23

Applicant: Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

Inventor： Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

IPC: H01L23/532

CPC classification number: H01L21/76811

Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.

Abstract translation: 公开了一种双镶嵌工艺。 提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。 介电层沉积在盖层上。 氧化硅层沉积在电介质层上。 在氧化硅层上形成金属硬掩模。 将沟槽开口蚀刻到金属硬掩模中。 部分通孔特征被蚀刻到沟槽开口内的电介质层中。 沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。 执行衬垫去除步骤以通过使用CF4 / NF3等离子体从双镶嵌开口选择性地去除暴露的盖层。

公开(公告)号：US07539058B2

公开(公告)日：2009-05-26

申请号：US11826600

申请日：2007-07-17

Applicant: Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

Inventor： Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

IPC: G11C11/34

CPC classification number: G11C16/10 ,  G11C16/3477

Abstract: A non-volatile memory and an operating method thereof. The non-volatile memory includes a memory cell array, a first dummy cell array, an address decoding unit and a synchronous programming circuit. The memory cell array includes a first memory cell, and the first dummy cell array includes a first dummy cell. The first dummy cell is adjacent to a first side of a memory cell array and corresponds to the first memory cell. The address decoding unit receives an address signal for decoding. When the address signal is a relative address of the first dummy cell, the synchronous programming circuit controls the first dummy cell and the first memory cell to be synchronously programmed.

公开(公告)号：US20090021980A1

公开(公告)日：2009-01-22

申请号：US11826600

申请日：2007-07-17

Applicant: Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

Inventor： Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

IPC: G11C16/06 ,  G11C8/00

CPC classification number: G11C16/10 ,  G11C16/3477

Abstract: A non-volatile memory and an operating method thereof. The non-volatile memory includes a memory cell array, a first dummy cell array, an address decoding unit and a synchronous programming circuit. The memory cell array includes a first memory cell, and the first dummy cell array includes a first dummy cell. The first dummy cell is adjacent to a first side of a memory cell array and corresponds to the first memory cell. The address decoding unit receives an address signal for decoding. When the address signal is a relative address of the first dummy cell, the synchronous programming circuit controls the first dummy cell and the first memory cell to be synchronously programmed.

Abstract translation: 非易失性存储器及其操作方法。 非易失性存储器包括存储单元阵列，第一虚拟单元阵列，地址解码单元和同步编程电路。 存储单元阵列包括第一存储单元，第一虚设单元阵列包括第一虚拟单元。 第一虚拟单元与存储单元阵列的第一侧相邻，并对应于第一存储单元。 地址解码单元接收用于解码的地址信号。 当地址信号是第一虚拟单元的相对地址时，同步编程电路控制第一虚设单元和第一存储单元进行同步编程。

公开(公告)号：US20070155157A1

公开(公告)日：2007-07-05

申请号：US11306590

申请日：2006-01-04

Applicant: Pei-Yu Chou ,  Chun-Jen Huang

Inventor： Pei-Yu Chou ,  Chun-Jen Huang

IPC: H01L21/4763

CPC classification number: H01L21/76844 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76829

Abstract: A process and structure for a metal interconnect comprises providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.

公开(公告)号：US08269548B2

公开(公告)日：2012-09-18

申请号：US13081472

申请日：2011-04-06

Applicant: Chun-Jen Huang

Inventor： Chun-Jen Huang

IPC: H01L35/00

CPC classification number: G05F3/30

Abstract: General speaking, a resistor of high resistivity has a negative-temperature-coefficient and a resistor of low resistivity has a positive-temperature-coefficient. Utilizing this characteristic, an appropriate proportion between the above resistors can be found to make a combined resistor with an approximate zero-temperature-coefficient. The combined resistor can be used to design a circuit for generating voltage and current with approximate zero-temperature-coefficients.

Abstract translation: 一般来说，高电阻率的电阻器具有负温度系数，低电阻率的电阻器具有正温度系数。 利用该特性，可以发现上述电阻器之间的适当比例使得具有近似零温度系数的组合电阻器。 组合电阻器可用于设计用于产生具有近似零温度系数的电压和电流的电路。

公开(公告)号：US07524742B2

公开(公告)日：2009-04-28

申请号：US11748472

申请日：2007-05-14

Applicant: Pei-Yu Chou ,  Chun-Jen Huang

Inventor： Pei-Yu Chou ,  Chun-Jen Huang

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L21/76844 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76829

Abstract: A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.

Abstract translation: 金属互连的工艺和结构包括：使用第一图案化硬掩模提供具有第一电导体的基板，形成第一介电层和第一图案化硬掩模，以形成第一开口和第二导电体，形成第二导体 电介质层和第二图案化硬掩模，使用第二图案化硬掩模作为蚀刻掩模，并使用第一图案化硬掩模作为蚀刻停止层以形成第二开口和第三导电体。

公开(公告)号：US20070090360A1

公开(公告)日：2007-04-26

申请号：US11415522

申请日：2006-05-02

Applicant: Sheng-Huei Dai ,  Ya-Chin King ,  Chun-Jen Huang ,  L.C. Kao

Inventor： Sheng-Huei Dai ,  Ya-Chin King ,  Chun-Jen Huang ,  L.C. Kao

IPC: H01L29/04 ,  H01L21/00 ,  H01L29/15 ,  H01L29/10 ,  H01L31/00 ,  H01L31/036

CPC classification number: H01L29/8611 ,  H01L29/66136

Abstract: Blanket implant diode which can be used for transient voltage suppression having a P+ substrate implanted with an N-type dopant blanket implant near a top surface of the substrate, creating a P− region. An oxide mask is layered adjacent to and above the P− region. The oxide mask is partially etched away from a portion of the P− region, creating an etched region. An N-type main function implant is implanted into the etched region, creating an N+ region above the P+ substrate and adjacent the P− region. And, a metal is layered above the oxide mask in the etched region to form an electrode. Terminations may be attached electrically to both sides of the P-N junction. Methods of making and using the present invention and methods for transient voltage suppression are also provided.

Abstract translation: 可以用于瞬态电压抑制的毯式注入二极管，其具有在衬底的顶表面附近注入N型掺杂剂覆盖层注入的P +衬底，形成P-区。 在P区附近层叠氧化物掩模。 氧化物掩模被部分地蚀刻离开P-区域的一部分，产生蚀刻区域。 将N型主要功能植入物注入到蚀刻区域中，在P +衬底上方形成N +区域并邻近P-区域。 并且，在蚀刻区域中的氧化物掩模上方形成金属以形成电极。 端子可以电连接到P-N结的两侧。 还提供了制造和使用本发明的方法和用于瞬态电压抑制的方法。