公开(公告)号：US07539058B2

公开(公告)日：2009-05-26

申请号：US11826600

申请日：2007-07-17

申请人： Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

发明人： Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/3477

摘要： A non-volatile memory and an operating method thereof. The non-volatile memory includes a memory cell array, a first dummy cell array, an address decoding unit and a synchronous programming circuit. The memory cell array includes a first memory cell, and the first dummy cell array includes a first dummy cell. The first dummy cell is adjacent to a first side of a memory cell array and corresponds to the first memory cell. The address decoding unit receives an address signal for decoding. When the address signal is a relative address of the first dummy cell, the synchronous programming circuit controls the first dummy cell and the first memory cell to be synchronously programmed.

公开(公告)号：US20090021980A1

公开(公告)日：2009-01-22

申请号：US11826600

申请日：2007-07-17

申请人： Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

发明人： Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

IPC分类号： G11C16/06 ,  G11C8/00

CPC分类号： G11C16/10 ,  G11C16/3477

摘要： A non-volatile memory and an operating method thereof. The non-volatile memory includes a memory cell array, a first dummy cell array, an address decoding unit and a synchronous programming circuit. The memory cell array includes a first memory cell, and the first dummy cell array includes a first dummy cell. The first dummy cell is adjacent to a first side of a memory cell array and corresponds to the first memory cell. The address decoding unit receives an address signal for decoding. When the address signal is a relative address of the first dummy cell, the synchronous programming circuit controls the first dummy cell and the first memory cell to be synchronously programmed.

摘要翻译： 非易失性存储器及其操作方法。 非易失性存储器包括存储单元阵列，第一虚拟单元阵列，地址解码单元和同步编程电路。 存储单元阵列包括第一存储单元，第一虚设单元阵列包括第一虚拟单元。 第一虚拟单元与存储单元阵列的第一侧相邻，并对应于第一存储单元。 地址解码单元接收用于解码的地址信号。 当地址信号是第一虚拟单元的相对地址时，同步编程电路控制第一虚设单元和第一存储单元进行同步编程。

公开(公告)号：US20080137427A1

公开(公告)日：2008-06-12

申请号：US11636920

申请日：2006-12-11

申请人： Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

发明人： Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

摘要： An embodiment of the present invention involves a method of programming a memory cell. The memory cell is in a first state having a maximum initial threshold voltage. The memory cell is to be programmed to one of a plurality of states having a higher target threshold voltage relative to the maximum initial threshold voltage. There is a cue voltage between the maximum initial threshold voltage and the target threshold voltage. The memory cell has a drain region. The method includes applying a drain voltage to the cell by a programming pulse having a first width, determining whether the cell has reached the cue threshold voltage, and if the cell has reached the cue threshold voltage, changing the programming pulse width from the first pulse width to a second pulse width. The second pulse width is smaller than the first pulse width.

摘要翻译： 本发明的一个实施例涉及一种编程存储器单元的方法。 存储单元处于具有最大初始阈值电压的第一状态。 存储器单元将被编程为具有相对于最大初始阈值电压的较高目标阈值电压的多个状态之一。 在最大初始阈值电压和目标阈值电压之间存在一个提示电压。 存储单元具有漏极区域。 该方法包括通过具有第一宽度的编程脉冲向单元施加漏极电压，确定单元是否已经达到提示阈值电压，以及如果单元已经达到提示阈值电压，则从第一脉冲改变编程脉冲宽度 宽度到第二个脉冲宽度。 第二脉冲宽度小于第一脉冲宽度。

公开(公告)号：US07474565B2

公开(公告)日：2009-01-06

申请号：US11636920

申请日：2006-12-11

申请人： Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

发明人： Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

摘要： An embodiment of the present invention involves a method of programming a memory cell. The memory cell is in a first state having a maximum initial threshold voltage. The memory cell is to be programmed to one of a plurality of states having a higher target threshold voltage relative to the maximum initial threshold voltage. There is a cue voltage between the maximum initial threshold voltage and the target threshold voltage. The memory cell has a drain region. The method includes applying a drain voltage to the cell by a programming pulse having a first width, determining whether the cell has reached the cue threshold voltage, and if the cell has reached the cue threshold voltage, changing the programming pulse width from the first pulse width to a second pulse width. The second pulse width is smaller than the first pulse width.

摘要翻译： 本发明的一个实施例涉及一种编程存储器单元的方法。 存储单元处于具有最大初始阈值电压的第一状态。 存储器单元将被编程为具有相对于最大初始阈值电压的较高目标阈值电压的多个状态之一。 在最大初始阈值电压和目标阈值电压之间存在一个提示电压。 存储单元具有漏极区域。 该方法包括通过具有第一宽度的编程脉冲向单元施加漏极电压，确定单元是否已经达到提示阈值电压，以及如果单元已经达到提示阈值电压，则从第一脉冲改变编程脉冲宽度 宽度到第二个脉冲宽度。 第二脉冲宽度小于第一脉冲宽度。

公开(公告)号：US20130285737A1

公开(公告)日：2013-10-31

申请号：US13460112

申请日：2012-04-30

申请人： Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

发明人： Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

IPC分类号： G05F3/02

CPC分类号： H02M3/07

摘要： In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.

摘要翻译： 在一个方面，第一电荷泵具有串联布置的电荷泵级。 相邻级之间的阶段节点由第二电荷泵泵送。 在另一方面，电荷泵级的定时由命令时钟信号控制。 命令时钟信号和命令数据在与电荷泵的集成电路和外部电路之间传送。

公开(公告)号：US20080171433A1

公开(公告)日：2008-07-17

申请号：US11621996

申请日：2007-01-11

申请人： Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

发明人： Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/768

CPC分类号： H01L21/76811

摘要： A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.

摘要翻译： 公开了一种双镶嵌工艺。 提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。 介电层沉积在盖层上。 氧化硅层沉积在电介质层上。 在氧化硅层上形成金属硬掩模。 将沟槽开口蚀刻到金属硬掩模中。 部分通孔特征被蚀刻到沟槽开口内的电介质层中。 沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。 执行衬垫去除步骤以通过使用CF 4 N 3 N 3等离子体从双镶嵌开口选择性地去除暴露的盖层。

公开(公告)号：US07378343B2

公开(公告)日：2008-05-27

申请号：US11164285

申请日：2005-11-17

申请人： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

发明人： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

IPC分类号： H01L21/4763

CPC分类号： H01L21/7681 ,  H01L21/76829

摘要： A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

摘要翻译： 双镶嵌工艺首先提供一种其上具有基底层的基底，嵌入底层的下部铜布线和覆盖嵌入的下部铜布线的下部盖层。 介电层沉积在下盖层上。 在电介质层上沉积TEOS基氧化物覆盖层。 TEOS基氧化物覆盖层的碳含量低于1×10 19原子/ cm 3。 金属硬掩模沉积在TEOS基氧化物覆盖层上。 将沟槽凹槽蚀刻到金属硬掩模和TEOS基氧化物盖层中。 然后将部分通孔特征通过沟槽凹槽蚀刻到TEOS基氧化物覆盖层和电介质层中。 沟槽凹槽和部分通孔特征被蚀刻转移到下面的电介质层中，从而形成一个双镶嵌开口，暴露下部铜布线的一部分。

公开(公告)号：US20070210454A1

公开(公告)日：2007-09-13

申请号：US11748472

申请日：2007-05-14

申请人： Pei-Yu Chou ,  Chun-Jen Huang

发明人： Pei-Yu Chou ,  Chun-Jen Huang

IPC分类号： H01L23/52

CPC分类号： H01L21/76844 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76829

摘要： A process and structure for a metal interconnect comprises providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.

摘要翻译： 用于金属互连的工艺和结构包括：使用第一图案化硬掩模提供具有第一电导体，形成第一介电层和第一图案化硬掩模的基板，以形成第一开口和第二导电体，形成第二导体 电介质层和第二图案化硬掩模，使用第二图案化硬掩模作为蚀刻掩模，并使用第一图案化硬掩模作为蚀刻停止层以形成第二开口和第三导电体。

公开(公告)号：US20070125750A1

公开(公告)日：2007-06-07

申请号：US11674678

申请日：2007-02-14

申请人： Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

发明人： Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

IPC分类号： C23F1/00 ,  H01L21/302 ,  B44C1/22

CPC分类号： H01L21/31144 ,  H01L21/02063 ,  H01L21/76811 ,  H01L21/76814 ,  Y10S438/906 ,  Y10S438/963

摘要： A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues.

摘要翻译： 低k绝缘膜沉积在晶片上。 然后在低k电介质膜上沉积金属层。 在金属层上形成抗蚀剂图案。 然后将抗蚀剂图案转移到下面的金属层以形成金属图案。 剥离抗蚀剂图案。 通过使用金属图案作为硬掩模将通孔等离子体蚀刻到低k电介质膜中。 等离子体蚀刻导致残留物沉积在通孔内。 然后进行湿处理以软化残留物。 进行等离子体干燥处理以破坏残留物。

公开(公告)号：US20070111514A1

公开(公告)日：2007-05-17

申请号：US11164285

申请日：2005-11-17

申请人： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

发明人： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

IPC分类号： H01L21/473

CPC分类号： H01L21/7681 ,  H01L21/76829

摘要： A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

摘要翻译： 双镶嵌工艺首先提供一种其上具有基底层的基底，嵌入底层的下部铜布线和覆盖嵌入的下部铜布线的下部盖层。 介电层沉积在下盖层上。 在电介质层上沉积TEOS基氧化物覆盖层。 TEOS基氧化物覆盖层的碳含量低于1×10 19原子/ cm 3。 金属硬掩模沉积在TEOS基氧化物覆盖层上。 将沟槽凹槽蚀刻到金属硬掩模和TEOS基氧化物盖层中。 然后将部分通孔特征通过沟槽凹槽蚀刻到TEOS基氧化物覆盖层和电介质层中。 沟槽凹槽和部分通孔特征被蚀刻转移到下面的电介质层中，从而形成一个双镶嵌开口，暴露下部铜布线的一部分。