公开(公告)号：US06748579B2

公开(公告)日：2004-06-08

申请号：US10231904

申请日：2002-08-30

申请人： Michael N. Dillon ,  Khosro Khakzadi ,  Scott A. Peterson

发明人： Michael N. Dillon ,  Khosro Khakzadi ,  Scott A. Peterson

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： A method is provided for fabricating an integrated circuit having a logical function. The method includes fabricating first and second routing layer masks and a first via mask. The first routing layer mask includes power supply segments and signal segments. The second routing layer mask includes signal segments and filler segments, wherein the filler segments are located in unused areas of the second routing layer mask. The first via mask defines vias that electrically couple the filler segments to the power supply segments. If the logical function is changed after the masks have been fabricated, a second via mask is fabricated. The second via mask decouples a filler segment from the power supply segments and couples the filler segment to a signal segment defined by the first routing layer mask to implement the logical function change. The integrated circuit is then fabricated with the first and second routing layer masks and the second via mask.

摘要翻译： 提供了一种用于制造具有逻辑功能的集成电路的方法。 该方法包括制造第一和第二路由层掩模和第一通孔掩模。 第一路由层掩码包括电源段和信号段。 第二路由层掩码包括信号段和填充段，其中填充段位于第二路由层掩码的未使用区域中。 第一个通孔掩模定义将填料段电耦合到电源段的通孔。 如果在制造掩模之后改变逻辑功能，则制造第二通孔掩模。 第二通孔掩模将填充段与电源段分离，并将填充段耦合到由第一路由层掩码定义的信号段，以实现逻辑功能改变。 然后利用第一和第二路由层掩模和第二通孔掩模制造集成电路。

公开(公告)号：US08429586B2

公开(公告)日：2013-04-23

申请号：US13424747

申请日：2012-03-20

申请人： Ramnath Venkatraman ,  Michael N. Dillon ,  David A. Gardner ,  Carl A. Monzel, III ,  Subramanian Ramesh ,  Robert C. Armstrong ,  Gary S. Delp ,  Scott A. Peterson

发明人： Ramnath Venkatraman ,  Michael N. Dillon ,  David A. Gardner ,  Carl A. Monzel, III ,  Subramanian Ramesh ,  Robert C. Armstrong ,  Gary S. Delp ,  Scott A. Peterson

IPC分类号： G06F17/50

CPC分类号： H03K19/1735 ,  G06F2217/64 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807

摘要： A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

摘要翻译： 提供了具有多个可固定晶体管的单元的基本单元电路架构，其可配置用于形成逻辑器件以及结构化ASIC内的单端口和双端口存储器件。 通过在固定结构上方形成可变互连层来实现随后的集成电路的不同配置。 电路架构可以实现单个单元或多个单元内的晶体管的互连。 互连可以配置成形成基本逻辑门，以及更复杂的数字和模拟子系统。 此外，每个单元包含可以可变地耦合以实现诸如SRAM器件的存储器件的晶体管的布局。 通过具有形成逻辑电路元件，存储器件或二者的能力，电路架构既是以内存为中心的，也是以逻辑为中心的，更能适应现代的SoC。

公开(公告)号：US20120175683A1

公开(公告)日：2012-07-12

申请号：US13424747

申请日：2012-03-20

申请人： Ramnath Venkatraman ,  Michael N. Dillon ,  David A. Gardner ,  Carl Anthony Monzel, III ,  Subramanian Ramesh ,  Robert C. Armstrong ,  Gary Scott Delp ,  Scott Allen Peterson

发明人： Ramnath Venkatraman ,  Michael N. Dillon ,  David A. Gardner ,  Carl Anthony Monzel, III ,  Subramanian Ramesh ,  Robert C. Armstrong ,  Gary Scott Delp ,  Scott Allen Peterson

IPC分类号： H01L27/105

CPC分类号： H03K19/1735 ,  G06F2217/64 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807

摘要： A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

摘要翻译： 提供了具有多个可固定晶体管的单元的基本单元电路架构，其可配置用于形成逻辑器件以及结构化ASIC内的单端口和双端口存储器件。 通过在固定结构上方形成可变互连层来实现随后的集成电路的不同配置。 电路架构可以实现单个单元或多个单元内的晶体管的互连。 互连可以配置成形成基本逻辑门，以及更复杂的数字和模拟子系统。 此外，每个单元包含可以可变地耦合以实现诸如SRAM器件的存储器件的晶体管的布局。 通过具有形成逻辑电路元件，存储器件或二者的能力，电路架构既是以内存为中心的，也是以逻辑为中心的，更能适应现代的SoC。

公开(公告)号：US20100097875A1

公开(公告)日：2010-04-22

申请号：US12254421

申请日：2008-10-20

申请人： David Vinke ,  Michael N. Dillon ,  Bret Alan Oeltjen ,  Uday Anumalachetty ,  Thomas Mathews Antisseril

发明人： David Vinke ,  Michael N. Dillon ,  Bret Alan Oeltjen ,  Uday Anumalachetty ,  Thomas Mathews Antisseril

IPC分类号： G11C5/14 ,  H01L21/60

CPC分类号： G11C5/063 ,  G11C8/10 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection structure coupled to the cells. Each of the standard cells includes first and second power rails adapted for connection to a voltage supply and a voltage return, respectively, of the standard cells. Each standard cell in a subset of the standard cells is arranged in direct abutment with at least two other standard cells, and at least first and second end cells are arranged in direct abutment with at least one other standard cell of the first plurality of standard cells. The power mesh power connection structure includes a plurality of conductive elements formed in a plurality of different conductive layers in the integrated circuit. The power mesh power connection structure is operative to connect the first and second power rails of the first plurality of standard cells to the voltage supply and voltage return, respectively, and is configured so as to reduce a first voltage differential between respective first power rails of the standard cells and to reduce a second voltage differential between respective second power rails of the standard cells.

摘要翻译： 用于向集成电路中的一个或多个标准单元分配功率的集成电路结构包括耦合到该单元的第一多个标准单元和功率网格功率连接结构。 每个标准单元包括分别连接到标准单元的电压源和电压返回的第一和第二电源轨。 标准细胞子集中的每个标准细胞被布置成与至少两个其它标准细胞直接邻接，并且至少第一和第二末端细胞被布置成与第一多个标准细胞的至少一个其它标准细胞直接邻接 。 功率网格功率连接结构包括形成在集成电路中的多个不同导电层中的多个导电元件。 功率网格电力连接结构可操作以将第一多个标准单元的第一和第二电力轨分别连接到电压供应和电压返回，并且被配置为减小相应的第一电力轨之间的第一电压差 并且减小标准单元的相应的第二电源轨之间的第二电压差。

公开(公告)号：US6093214A

公开(公告)日：2000-07-25

申请号：US31956

申请日：1998-02-26

申请人： Michael N. Dillon

发明人： Michael N. Dillon

IPC分类号： G06F17/50 ,  H01L27/118

CPC分类号： H01L27/11807 ,  G06F17/5068

摘要： A method of forming a layout definition of a semiconductor integrated circuit includes generating a netlist of functionally committed standard cell instances and the electrical interconnections between the standard cell instances. The standard cell instances are then placed in a layout pattern. Also, functionally uncommitted base cells are place with the standard cell instances in the layout pattern. The base cell instances may be metalized, if needed, in later processing steps to implement design changes by adding additional logical functions.

摘要翻译： 形成半导体集成电路的布局定义的方法包括生成功能承诺标准单元实例的网表和标准单元实例之间的电互连。 然后将标准单元格实例放置在布局模式中。 而且，功能上未提交的基本单元格与布局模式中的标准单元格实例一起放置。 如果需要，基本单元实例可以在稍后的处理步骤中进行金属化，以通过添加附加的逻辑功能来实现设计更改。