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    Management of parity data in a memory sub-system
    12.
    发明授权
    Management of parity data in a memory sub-system 有权

    公开(公告)号：US11630725B2

    公开(公告)日：2023-04-18

    申请号：US16834534

    申请日：2020-03-30

    Applicant: Micron Technology, Inc.

    Inventor： Amit Bhardwaj ,  Naveen Bolisetty ,  Suman Kumari

    IPC: G06F11/00 ,  G06F11/10 ,  G06F9/30 ,  G06F12/02 ,  G06F12/0882

    Abstract: Host data is written to a set of pages of a page stripe of a storage area of a memory sub-system. A set of exclusive or (XOR) parity values corresponding to the host data written to a portion of the set of pages of the storage area is generated. An additional XOR parity value is generated by executing an XOR operation using the set of XOR parity values. Parity data including the set of XOR parity values and the additional XOR parity value is stored in a cache memory of the memory sub-system. The parity data is written to an available page stripe of the storage area.

    Remapping bad blocks in a memory sub-system
    13.
    发明授权
    Remapping bad blocks in a memory sub-system 有权

    公开(公告)号：US11605439B2

    公开(公告)日：2023-03-14

    申请号：US17218385

    申请日：2021-03-31

    Applicant: Micron Technology, Inc.

    Inventor： Amit Bhardwaj

    IPC: G11C29/00 ,  G11C29/40 ,  G11C29/42 ,  G11C29/44

    Abstract: Disclosed is a system that comprises a memory device comprising a plurality of memory planes and a processing device, operatively coupled with the memory device, to perform operations that include, generating a block stripe of the memory device, wherein the block stripe comprises a plurality of blocks arranged across the plurality of memory planes; determining that a first block of the plurality of blocks of the block stripe is associated with an error condition, wherein the first block is associated with a first plane of the plurality of planes; and responsive to determining that the first block of the plurality of blocks of the block stripe is associated with the error condition, performing an error recovery operation on the plurality of blocks to replace the first block with a replacement block in the block stripe.

    BLOCK ALLOCATION AND ERASE TECHNIQUES FOR SEQUENTIALLY-WRITTEN MEMORY DEVICES
    14.
    发明申请
    BLOCK ALLOCATION AND ERASE TECHNIQUES FOR SEQUENTIALLY-WRITTEN MEMORY DEVICES 有权

    公开(公告)号：US20230028627A1

    公开(公告)日：2023-01-26

    申请号：US17381945

    申请日：2021-07-21

    Applicant: Micron Technology, Inc.

    Inventor： Amit Bhardwaj

    IPC: G06F3/06

    Abstract: A plurality of zone reset counters and a global reset counter are maintained. A zone reset counter represents a number of times a respective zone of a memory device has been reset. The global reset counter represents a measure of central tendency of the plurality of zone reset counters. A write command directed to a target zone of the memory device is received, and responsive to determining that a target portion of the target zone is not open, a value of the zone reset counter of het target zone is compared to the value of the global reset counter. If the value of the target zone reset counter equals or exceeds the value of the global reset counter, a portion from a free block list is allocated to the target zone. The allocated portion has a highest program erase count among the one or more portions in free block list.

    Remapping bad blocks in a memory sub-system
    15.
    发明授权
    Remapping bad blocks in a memory sub-system 有权

    公开(公告)号：US12217814B2

    公开(公告)日：2025-02-04

    申请号：US18103183

    申请日：2023-01-30

    Applicant: Micron Technology, Inc.

    Inventor： Amit Bhardwaj

    IPC: G11C29/00 ,  G06F3/06 ,  G11C29/40 ,  G11C29/42 ,  G11C29/44

    Abstract: Disclosed is a system that comprises a memory device comprising a plurality of memory planes and a processing device, operatively coupled with the plurality of memory planes, to perform operations that include, identifying a first block residing on a memory plane of the memory device, wherein the first block is associated with an error condition; and responsive to identifying the first block, performing an error recovery operation to replace the first block with a second block, wherein the second block resides on the memory plane.

    REMAPPING BAD BLOCKS IN A MEMORY SUB-SYSTEM
    17.
    发明公开
    REMAPPING BAD BLOCKS IN A MEMORY SUB-SYSTEM 审中-公开

    公开(公告)号：US20240256132A1

    公开(公告)日：2024-08-01

    申请号：US18103183

    申请日：2023-01-30

    Applicant: Micron Technology, Inc.

    Inventor： Amit Bhardwaj

    IPC: G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679

    Abstract: Disclosed is a system that comprises a memory device comprising a plurality of memory planes and a processing device, operatively coupled with the plurality of memory planes, to perform operations that include, identifying a first block residing on a memory plane of the memory device, wherein the first block is associated with an error condition; and responsive to identifying the first block, performing an error recovery operation to replace the first block with a second block, wherein the second block resides on the memory plane.

    Zone-aware memory management in memory sub-systems
    18.
    发明授权
    Zone-aware memory management in memory sub-systems 有权

    公开(公告)号：US11960409B2

    公开(公告)日：2024-04-16

    申请号：US18094744

    申请日：2023-01-09

    Applicant: Micron Technology, Inc.

    Inventor： Amit Bhardwaj

    IPC: G06F12/10 ,  G06F12/02

    CPC classification number: G06F12/10 ,  G06F12/0253 ,  G06F2212/1044 ,  G06F2212/657

    Abstract: Disclosed is a system including a memory device having a plurality of physical memory blocks and associated with a logical address space that comprises a plurality of zones, wherein each zone comprises a plurality of logical block addresses (LBAs), and a processing device, operatively coupled with the memory device, to perform operations of receiving a request to store data referenced by an LBA associated with a first zone of the plurality of zones, obtaining a version identifier of the first zone, obtaining erase values for a plurality of available physical memory blocks of the memory device, selecting, in view of the version identifier of the first zone and the erase values, a first physical memory block of the plurality of available physical memory blocks, mapping a next available LBA within the first zone to the first physical memory block, and storing the data in the first physical memory block.

    ZONE-AWARE MEMORY MANAGEMENT IN MEMORY SUB-SYSTEMS
    20.
    发明申请
    ZONE-AWARE MEMORY MANAGEMENT IN MEMORY SUB-SYSTEMS 有权

    公开(公告)号：US20210397562A1

    公开(公告)日：2021-12-23

    申请号：US16946377

    申请日：2020-06-18

    Applicant: Micron Technology, Inc.

    Inventor： Amit Bhardwaj

    IPC: G06F12/10 ,  G06F12/02

    Abstract: Disclosed is a system including a memory device having a plurality of physical memory blocks and associated with a logical address space that comprises a plurality of zones, wherein each zone comprises a plurality of logical block addresses (LBAs), and a processing device, operatively coupled with the memory device, to perform operations of receiving a request to store data referenced by an LBA associated with a first zone of the plurality of zones, obtaining a version identifier of the first zone, obtaining erase values for a plurality of available physical memory blocks of the memory device, selecting, in view of the version identifier of the first zone and the erase values, a first physical memory block of the plurality of available physical memory blocks, mapping a next available LBA within the first zone to the first physical memory block, and storing the data in the first physical memory block.

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