公开(公告)号：US20240427511A1

公开(公告)日：2024-12-26

申请号：US18828263

申请日：2024-09-09

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Brian Toronyi

IPC: G06F3/06

Abstract: A first memory resource is configured to store a data structure. The first memory resource is coupled to a second memory resource that is configured to store a plurality of data structures. A processing device is coupled to the first memory resource, the second memory resource, and a third memory resource. The processing device writes data entries to the data structure within the first memory resource, determine that the data structure within the first memory resource includes a threshold quantity of data entries, and write the contents of the data structure within the first memory resource to a data structure within the second memory resource. The processing resource is further configured to move the contents of the contents of the data structure in the second memory resource to the third memory resource by readdressing the entries written within the second memory resource to virtual addresses associated with the third memory resource.

公开(公告)号：US12086440B2

公开(公告)日：2024-09-10

申请号：US17867396

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Brian Toronyi

IPC: G06F3/06

CPC classification number: G06F3/0638 ,  G06F3/061 ,  G06F3/0683

Abstract: A first memory resource is configured to store a data structure. The first memory resource is coupled to a second memory resource that is configured to store a plurality of data structures. A processing device is coupled to the first memory resource, the second memory resource, and a third memory resource. The processing device writes data entries to the data structure within the first memory resource, determine that the data structure within the first memory resource includes a threshold quantity of data entries, and write the contents of the data structure within the first memory resource to a data structure within the second memory resource. The processing resource is further configured to move the contents of the contents of the data structure in the second memory resource to the third memory resource by readdressing the entries written within the second memory resource to virtual addresses associated with the third memory resource.

公开(公告)号：US20240264743A1

公开(公告)日：2024-08-08

申请号：US18636783

申请日：2024-04-16

Applicant: Micron Technology, Inc.

Inventor： Brian Toronyi ,  Scheheresade Virani

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F3/0608 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/1009

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a memory access request specifying a logical address of a data item and a memory access operation to be performed with respect to the data item; produce a truncated logical address by applying a predefined mathematical transformation to the specified logical address; identifying, in an address translation table, an address translation table entry identified by the truncated logical address; and perform the memory access operation using a physical address specified by the address translation table entry.

公开(公告)号：US11960754B2

公开(公告)日：2024-04-16

申请号：US17412830

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Revanth Kamaraj ,  Brian Toronyi ,  Balwinder Pal Sethi ,  Trapti Jain ,  Madhu ,  Chandrakanth Rapalli

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A logical array having a plurality of memory banks is constructed, wherein each of the plurality of memory banks is split into a plurality of slots. A plurality of elements corresponding to a plurality of data components are stored in the plurality of slots of each of the plurality of memory banks of the logical array. The location of a data component stored in the memory component is determined by locating elements stored in a particular slot of the plurality of slots; and performing a corrective search on the located elements in the particular slot to locate a particular element. The data component is accessed based on the location of the particular element.

公开(公告)号：US20230393981A1

公开(公告)日：2023-12-07

申请号：US17946960

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Steven R. Narum ,  Brian Toronyi

IPC: G06F12/0804 ,  G06F12/02 ,  G06F12/1027

CPC classification number: G06F12/0804 ,  G06F12/0246 ,  G06F12/1027

Abstract: Apparatus and methods include receiving signaling indicative of performance of an operation to update a plurality of data entries written to a memory device and having a same offset from an initial physical address corresponding to each of the plurality of data entries and performing the operation to write the update to the plurality of data entries written to the memory device and having the same offset from the initial physical address corresponding to each of the plurality of data entries responsive to receiving the signaling indicative of performance of the operation to update the plurality of data entries.