公开(公告)号：US09274883B2

公开(公告)日：2016-03-01

申请号：US14520732

申请日：2014-10-22

Applicant: Micron Technology, Inc.

Inventor： Steven R. Narum

IPC: G06F11/10 ,  G06F12/06 ,  G06F12/10

CPC classification number: G06F11/1008 ,  G06F11/1068 ,  G06F12/06 ,  G06F12/10

Abstract: Apparatuses and methods for storing a validity mask and operating apparatuses are described. A number of methods for operating an apparatus include storing a validity mask that is associated with a number of pages of memory cells in a group of pages and that provides validity information for the number of pages of memory cells in the group of pages.

Abstract translation: 描述用于存储有效性掩模和操作装置的装置和方法。 用于操作设备的多种方法包括存储与一组页面中的多页存储器单元相关联的有效性掩码，并且提供页组中的存储器单元的页数的有效性信息。

公开(公告)号：US20150100853A1

公开(公告)日：2015-04-09

申请号：US14520732

申请日：2014-10-22

Applicant: Micron Technology, Inc.

Inventor： Steven R. Narum

IPC: G06F11/10

CPC classification number: G06F11/1008 ,  G06F11/1068 ,  G06F12/06 ,  G06F12/10

Abstract: Apparatuses and methods for storing a validity mask and operating apparatuses are described. A number of methods for operating an apparatus include storing a validity mask that is associated with a number of pages of memory cells in a group of pages and that provides validity information for the number of pages of memory cells in the group of pages.

Abstract translation: 描述用于存储有效性掩模和操作装置的装置和方法。 用于操作设备的多种方法包括存储与一组页面中的多页存储器单元相关联的有效性掩码，并且提供页组中的存储器单元的页数的有效性信息。

公开(公告)号：US12105621B2

公开(公告)日：2024-10-01

申请号：US17930117

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Steven R. Narum ,  Huapeng Guan

IPC: G06F12/02 ,  G06F1/3225

CPC classification number: G06F12/0246 ,  G06F1/3225 ,  G06F12/0292 ,  G06F2212/205 ,  G06F2212/7201

Abstract: A memory device may detect a memory operation that updates a level two volatile (L2V) entry stored in an L2V table. Each L2V entry in the L2V table may indicate a mapping between a respective logical block address (LBA) and a respective user data physical address in non-volatile memory. The memory operation may cause a mapping between an LBA indicated in the L2V entry and a user data physical address indicated in the L2V entry to become invalid. The memory device may store, in a volatile memory log, an indication of an LBA region that includes the LBA. The memory device may detect that an L2 transfer condition, associated with the volatile memory log, is satisfied. The memory device may copy, from volatile memory to non-volatile memory, every L2V entry that indicates an LBA included in the LBA region based on detecting that the L2 transfer condition is satisfied.

公开(公告)号：US20230393981A1

公开(公告)日：2023-12-07

申请号：US17946960

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Steven R. Narum ,  Brian Toronyi

IPC: G06F12/0804 ,  G06F12/02 ,  G06F12/1027

CPC classification number: G06F12/0804 ,  G06F12/0246 ,  G06F12/1027

Abstract: Apparatus and methods include receiving signaling indicative of performance of an operation to update a plurality of data entries written to a memory device and having a same offset from an initial physical address corresponding to each of the plurality of data entries and performing the operation to write the update to the plurality of data entries written to the memory device and having the same offset from the initial physical address corresponding to each of the plurality of data entries responsive to receiving the signaling indicative of performance of the operation to update the plurality of data entries.

公开(公告)号：US08996907B2

公开(公告)日：2015-03-31

申请号：US14050774

申请日：2013-10-10

Applicant: Micron Technology, Inc.

Inventor： Christian M. Gyllenskog ,  Phil W. Lee ,  Steven R. Narum

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/0787 ,  G06F11/1044 ,  G06F11/108

Abstract: Methods, devices, and systems for determining location of error detection data are described. One method for operating a memory unit having a bad group of memory cells includes determining a location of where to store error detection data for data to be stored across a plurality of memory units, including the memory unit having the bad group, based at least partially on a location of the bad group and storing the error detection data in the determined location.

Abstract translation: 描述用于确定错误检测数据的位置的方法，装置和系统。 用于操作具有不良组的存储器单元的存储器单元的一种方法包括：至少部分地确定在多个存储器单元（包括具有不良组的存储器单元）中存储要被存储的数据的位置的位置， 在坏组的位置上，并将错误检测数据存储在确定的位置。

公开(公告)号：US20140149804A1

公开(公告)日：2014-05-29

申请号：US14050774

申请日：2013-10-10

Applicant: Micron Technology, Inc.

Inventor： Christian M. Gyllenskog ,  Phil W. Lee ,  Steven R. Narum

IPC: G06F11/07

CPC classification number: G06F11/0787 ,  G06F11/1044 ,  G06F11/108

Abstract: Methods, devices, and systems for determining location of error detection data are described. One method for operating a memory unit having a bad group of memory cells includes determining a location of where to store error detection data for data to be stored across a plurality of memory units, including the memory unit having the bad group, based at least partially on a location of the bad group and storing the error detection data in the determined location.

Abstract translation: 描述用于确定错误检测数据的位置的方法，装置和系统。 用于操作具有不良组的存储器单元的存储器单元的一种方法包括：至少部分地确定在多个存储器单元（包括具有不良组的存储器单元）中存储要被存储的数据的位置的位置， 在坏组的位置上，并将错误检测数据存储在确定的位置。

公开(公告)号：US12235764B2

公开(公告)日：2025-02-25

申请号：US17946960

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Steven R. Narum ,  Brian Toronyi

IPC: G06F12/10 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/1027

Abstract: Apparatus and methods include receiving signaling indicative of performance of an operation to update a plurality of data entries written to a memory device and having a same offset from an initial physical address corresponding to each of the plurality of data entries and performing the operation to write the update to the plurality of data entries written to the memory device and having the same offset from the initial physical address corresponding to each of the plurality of data entries responsive to receiving the signaling indicative of performance of the operation to update the plurality of data entries.

公开(公告)号：US20240126467A1

公开(公告)日：2024-04-18

申请号：US18395934

申请日：2023-12-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Steven R. Narum

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679

Abstract: One or more data items is received by a processing device managing one or more memory devices partitioned into a plurality of die partitions. The one or more data items is determined to be written sequentially to one or more blocks within a die partition of the plurality of die partitions. Metadata associated with the one or more data items is written sequentially to one or more blocks across the plurality of die partitions.