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公开(公告)号：US20250028373A1
公开(公告)日：2025-01-23
申请号：US18773178
申请日：2024-07-15
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Eyal En Gad , Leonid Minz , Sivagnanam Parthasarathy
Abstract: A method includes generating, by circuitry resident on a memory device, parity information, appending parity information to data read from the memory device to generate a bit string comprising the data read from the memory device and parity information, transmitting the bit string from the memory device to a physical input/output (PHY I/O) device couplable to the memory device via a channel, calculating a parity mismatch value based on a comparison between received memory parity information and a calculated PHY I/O parity information, determining a target parity mismatch value, comparing the calculated parity mismatch value and the determined target parity mismatch value, and regulating a voltage in response to the comparison between the calculated parity mismatch value and the target parity mismatch value to maintain an actual channel error rate within an optimal range.
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公开(公告)号：US12164375B2
公开(公告)日：2024-12-10
申请号：US17949655
申请日：2022-09-21
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Eyal En Gad , Fan Zhou
IPC: G06F11/10 , G06F7/501 , G06F11/07 , G11C29/44 , G11C29/52 , H03M13/11 , H03M13/15 , H03M13/29 , H03M13/37 , H03M13/45
Abstract: A method includes determining a quantity of errors for a bit string based on a quantity of bits having a logical value of one within the bit string and writing an indication corresponding to the quantity of errors for the bit string to an array of memory cells. The method can further include determining that the quantity of errors for the bit string has reached a threshold quantity of errors and refraining from performing a subsequent operation to determine the quantity of errors for the bit string in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.
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公开(公告)号：US12088301B2
公开(公告)日：2024-09-10
申请号：US17696352
申请日：2022-03-16
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Yoav Weinberg
Abstract: A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.
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公开(公告)号：US20240185898A1
公开(公告)日：2024-06-06
申请号：US18523366
申请日：2023-11-29
Applicant: Micron Technology, Inc.
Inventor： Eyal En Gad , Leon Zlotnik , Yoav Weinberg
CPC classification number: G11C7/1012 , G06F11/1068 , G11C7/1039
Abstract: A method includes receiving, by shift circuitry, a bit string comprising a plurality of bits and determining, based on a shifting indicator, a quantity of bits by which the bit string is to be shifted within the shift circuitry. The method further includes generating a shifted bit string by performing, by the shift circuitry, an operation to shift the bit string by the quantity of bits indicated by the shifting indicator and performing, by decision circuitry coupled to the shift circuitry, an operation to alter one or more of the plurality of bits of the shifted bit string from a logical value of one to a logical value of zero or from a logical value of zero to a logical value of one.
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公开(公告)号：US20240020223A1
公开(公告)日：2024-01-18
申请号：US17867375
申请日：2022-07-18
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Brian Toronyi
CPC classification number: G06F12/023 , G06F9/5016 , G06F12/0292
Abstract: A first data entry is written to an address location of a memory resource that is neither a first physical address of the memory resource nor a last physical address of the memory resource. In response to a determination that a second data entry has a value that is greater than a value associated with the first data entry, the second data entry is written to an address location of the memory resource that is physically located between the address location of the memory resource to which the first data entry is written and the last physical address of the memory resource. In contrast, in response to a determination that the second data entry has the value that is less than the value associated with the first data entry, the second data entry is written to an address location of the memory resource that is physically located between the address location of the memory resource to which the first data entry is written and the first physical address of the memory resource.
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Patent Agency Ranking
公开(公告)号：US11747842B1
公开(公告)日：2023-09-05
申请号：US17717599
申请日：2022-04-11
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Ekram H. Bhuiyan
Abstract: Aspects of the present disclosure are directed to multi-referenced power supplies. One method includes sensing each voltage, via a voltage sensor, of plurality of voltages from different areas of circuit components prior to the voltage reaching a voltage regulator, receiving, at a voltage manager, a sensed voltage magnitude from the voltage sensor, and selecting a feedback voltage to be provided to the voltage regulator based on the sensed voltage magnitude from the voltage sensor for the at least one of the plurality of voltages.
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公开(公告)号：US20250069679A1
公开(公告)日：2025-02-27
申请号：US18774638
申请日：2024-07-16
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz
Abstract: A method includes determining a target total bit-error-rate (BER), calculating a target channel BER based on the target total BER, and training a channel to the calculated target channel BER by transmitting data over the channel in a loop from a physical input/output (PHY I/O) to a memory device, transmitting the test data over the channel in the loop from the memory device to the PHY I/O, wherein the data is looped from the memory device and back to the PHY I/O without being written to or road from the memory device, determining an actual channel BER based on the data transmitted to and received from the memory device, comparing the actual channel BER to the calculated target channel BER, and regulating a voltage value based on the comparison.
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公开(公告)号：US20240429904A1
公开(公告)日：2024-12-26
申请号：US18826526
申请日：2024-09-06
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Yoav Weinberg
Abstract: A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.
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公开(公告)号：US20240427511A1
公开(公告)日：2024-12-26
申请号：US18828263
申请日：2024-09-09
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Brian Toronyi
IPC: G06F3/06
Abstract: A first memory resource is configured to store a data structure. The first memory resource is coupled to a second memory resource that is configured to store a plurality of data structures. A processing device is coupled to the first memory resource, the second memory resource, and a third memory resource. The processing device writes data entries to the data structure within the first memory resource, determine that the data structure within the first memory resource includes a threshold quantity of data entries, and write the contents of the data structure within the first memory resource to a data structure within the second memory resource. The processing resource is further configured to move the contents of the contents of the data structure in the second memory resource to the third memory resource by readdressing the entries written within the second memory resource to virtual addresses associated with the third memory resource.
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公开(公告)号：US12169431B2
公开(公告)日：2024-12-17
申请号：US17893850
申请日：2022-08-23
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik
IPC: G06F1/3296 , G06F1/324
Abstract: An example method for voltage frequency scaling based on error rate can include performing a plurality of monitoring operations on a system on chip (SoC) at a respective plurality of voltage values (and/or plurality of frequency values and/or temperature values). The example method can include causing error rate data gathered from each of the plurality of monitoring operations to be entered into a database, wherein the entered error rate data is associated with the plurality of voltage values. The entered data is associated with the respective plurality of voltage value. The example method can include generating a plot using the error rate date in the database. The example method can include determining a particular voltage value greater than each of the plurality of voltage values based on the plot and a particular error rate associated with the particular voltage value.
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