公开(公告)号：US20240069984A1

公开(公告)日：2024-02-29

申请号：US17823468

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Christopher Baronne ,  Tony M. Brewer

IPC: G06F9/54 ,  G06F9/30

CPC classification number: G06F9/542 ,  G06F9/3009

Abstract: Devices and techniques for asynchronous event message handing in a processor are described herein. A barrel multithreaded processor may include an asynchronous event handler to receive an indication of a thread create instruction from a parent thread, determine a return value size of return values from the indication of the thread create instruction, determine whether sufficient space exists in the memory to store the return values, allocate space in the memory to store the return parameters in response to determining that there is sufficient space in the memory to store the return values, and provide access to the return values from the allocated space to the parent thread based at least in part on a thread return instruction from the child thread.

公开(公告)号：US20240028526A1

公开(公告)日：2024-01-25

申请号：US17813780

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： Christopher Baronne ,  Tony M. Brewer

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1668 ,  G06F13/4027

Abstract: Various examples are directed to systems and methods for requesting an atomic operation. A first hardware compute element may send a first request via a network structure, where the first request comprises an atomic opcode indicating an atomic operation to be performed by a second hardware compute element. The network structure may provide an address bus from the first hardware compute element for providing the atomic opcode to the second hardware compute element. The second hardware compute element may execute the atomic operation and send confirmation data indicating completion of the atomic operation. The network structure may provide a second bus from the second hardware compute element and the first hardware compute element. The second bus may be for providing the confirmation data from the second hardware compute element to the first hardware compute element.

公开(公告)号：US20240028390A1

公开(公告)日：2024-01-25

申请号：US17813763

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： Christopher Baronne ,  Michael Keith Dugan ,  Bryan Hornung

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F9/505

Abstract: Various examples are directed to an arrangement comprising a first hardware compute element and a hardware balancer element. The first hardware compute element may send a first request message to a hardware balancer element. The first request message may describe a processing task. The hardware balancer element may send a second request message towards a second hardware compute element for executing the processing task and send to the first compute element a first reply message in reply to the first request message. After sending the first reply message, the hardware balancer element may receive a first completion request message indicating that the processing task is assigned and send, to the first hardware computing element, a second completion request message, the second completion request message indicating that the processing task is assigned.

公开(公告)号：US20240028206A1

公开(公告)日：2024-01-25

申请号：US17813800

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： Christopher Baronne ,  Dean E. Walker ,  Bryan Hornung

IPC: G06F3/06 ,  G06F12/0802

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0802 ,  G06F2212/1024

Abstract: Various examples are directed to systems and methods for executing a transaction between hardware compute elements of a computing system. A first hardware compute element may send a first write request to a second hardware compute element via a network structure. The first write request may comprise first source identifier data describing the first hardware compute element and first payload data describing a processing task requested by the first hardware compute element. The network structure may store first write request state data describing the first write request. Before the processing task is completed, the second hardware compute element may send a first write confirm message.

公开(公告)号：US11614942B2

公开(公告)日：2023-03-28

申请号：US17074739

申请日：2020-10-20

Applicant: Micron Technology, Inc.

Inventor： Christopher Baronne ,  Dean E. Walker

IPC: G06F9/38 ,  G06F7/57 ,  G06F9/30 ,  G06F13/16

Abstract: Devices and techniques for short-thread rescheduling in a processor are described herein. When an instruction for a thread completes, a result is produced. The condition that the same thread is scheduled in a next execution slot and that the next instruction of the thread will use the result can be detected. In response to this condition, the result can be provided directly to an execution unit for the next instruction.