公开(公告)号：US20240282691A1

公开(公告)日：2024-08-22

申请号：US18652515

申请日：2024-05-01

Applicant: Micron Technology, Inc.

Inventor： David K. Ovard ,  Thomas Hein ,  Timothy M. Hollis ,  Walter L. Moden

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: Systems may include a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA), or any combination thereof. At least one memory device may be connected to the CPU, the GPU, or the FPGA. The memory device(s) may include a device substrate including a microelectronic device and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on the package substrate. Each ball of the ball grid array positioned and configured to carry one of a high-bandwidth data signal or a high-frequency clock signal may be located only diagonally adjacent to any other balls of the ball grid array configured to carry another of a high-bandwidth data signal or a high-frequency clock signal.

公开(公告)号：US20240105574A1

公开(公告)日：2024-03-28

申请号：US17936278

申请日：2022-09-28

Applicant: Micron Technology, Inc.

Inventor： M. Ataul Karim ,  David K. Ovard

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/14 ,  H01L23/15 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49833 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0655 ,  H01L24/16 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434

Abstract: An interposer includes an upper surface for coupling to a chip, a lower surface for coupling to a package substrate, and redistribution layers between the upper surface and the lower surface and including routed conductive lines. A respective one of the routed conductive lines extend between a first location and a second location and includes two or more traces extending substantially in parallel between the first location and the second location. Related devices and methods are also described.

公开(公告)号：US11670578B2

公开(公告)日：2023-06-06

申请号：US17334447

申请日：2021-05-28

Applicant: Micron Technology, Inc.

Inventor： David K. Ovard ,  Thomas Hein ,  Timothy M. Hollis ,  Walter L. Moden

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: Apparatuses may include a device substrate including a microelectronic device and bond pads proximate to an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball positioned and configured to carry a high-bandwidth data signal or a high-frequency clock signal may be located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry a high-bandwidth data signal or a high-frequency clock signal. Each ball positioned and configured to carry a high-bandwidth data signal may be located only diagonally adjacent to any other balls configured to carry a high-bandwidth data signal or a high-frequency clock signal.