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    MEMORY DEVICE PERFORMING SIGNED MULTIPLICATION USING SETS OF TWO MEMORY CELLS
    11.
    发明公开
    MEMORY DEVICE PERFORMING SIGNED MULTIPLICATION USING SETS OF TWO MEMORY CELLS 审中-公开

    公开(公告)号：US20240303296A1

    公开(公告)日：2024-09-12

    申请号：US18423163

    申请日：2024-01-25

    Applicant: Micron Technology, Inc.

    Inventor： Hernan Castro

    IPC: G06F17/16

    CPC classification number: G06F17/16

    Abstract: Systems, methods, and apparatus related to memory devices that perform signed multiplication using sets each containing two memory cells. In one approach, sets organized as pairs of memory cells in a memory cell array are programmed so that each set stores a signed weight. Voltages are applied to the sets of memory cells at first and second times. The voltages represent signed inputs to be multiplied by the signed weights. Output currents from the memory cells in each set are accumulated at the first and second times in a respective common line for each set. A signed result for each set is provided based on digitizing sums of the output currents accumulated at the first and second times.

    MEMORY DEVICE FOR MULTIPLICATION USING MEMORY CELLS HAVING DIFFERENT BIAS LEVELS BASED ON BIT SIGNIFICANCE
    12.
    发明公开
    MEMORY DEVICE FOR MULTIPLICATION USING MEMORY CELLS HAVING DIFFERENT BIAS LEVELS BASED ON BIT SIGNIFICANCE 审中-公开

    公开(公告)号：US20240303039A1

    公开(公告)日：2024-09-12

    申请号：US18423186

    申请日：2024-01-25

    Applicant: Micron Technology, Inc.

    Inventor： Hernan Castro

    IPC: G06F7/523

    CPC classification number: G06F7/523

    Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using logic states of memory cells. In one approach, a memory cell array has memory cells that are each programmed to store one bit of a multi-bit weight. Voltage drivers apply different voltages to the memory cells during multiplication. The magnitudes of the different voltages correspond to a significance of the bit stored by the respective memory cell. One or more inputs are applied to the memory cells to multiply the inputs by the multi-bit weight. Output currents from the memory cells are summed on a common line. The sum of the output currents is used to provide at least one result from the multiplication.

    APPARATUSES AND METHODS FOR EFFICIENT WRITE IN A CROSS-POINT ARRAY
    15.
    发明申请
    APPARATUSES AND METHODS FOR EFFICIENT WRITE IN A CROSS-POINT ARRAY 有权
    用于在跨点阵列中有效写入的装置和方法

    公开(公告)号：US20150187417A1

    公开(公告)日：2015-07-02

    申请号：US14591800

    申请日：2015-01-07

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Hernan Castro

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/77

    Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.

    Abstract translation: 包括存储器阵列（诸如交叉点阵列）的存储器电路可以包括可以同时用作选择元件/驱动器和去选择元件/驱动器的电路元件。 选择/取消选择驱动器可以用于提供选择功能以及操作功能。 操作功能可以包括为存储器阵列中的写入和/或读取操作提供足够的电流和电压。 当选择路径用于提供操作功能时，可以实现高效的交叉点实现。 操作功能可以通过去选择电源和/或去选择元件的电路操作来实现。

    Truncated Resolution for Time Sliced Computation of Multiplication and Accumulation using a Memory Cell Array
    16.
    发明申请
    Truncated Resolution for Time Sliced Computation of Multiplication and Accumulation using a Memory Cell Array 有权

    公开(公告)号：US20250061930A1

    公开(公告)日：2025-02-20

    申请号：US18751094

    申请日：2024-06-21

    Applicant: Micron Technology, Inc.

    Inventor： Hernan Castro

    IPC: G11C7/16 ,  G11C7/10 ,  G11C7/12 ,  G11C8/08

    Abstract: A memory sub-system configured to perform multiplication and accumulation operations using truncated outputs. For example, voltages can be applied, according to a bit slice having a slice weight in an input, to memory cells storing weights. A resolution control can be applied, according to the slice weight, to an analog to digital converter coupled to the line having a current resulting from the memory cells responsive to the voltages. The analog to digital converter can measure at least one first bit of a quantity representative of a magnitude of the current in the line to provide a truncated output, skipping measuring of at least one second bit of the quantity according to the resolution control. Summing truncated outputs resulting from the bit slices from the input can provide an approximated result of the sum of elements in the input weighted by the weights.

    MEMORY DEVICE FOR SIGNED MULTI-BIT TO MULTI-BIT MULTIPLICATIONS
    17.
    发明公开
    MEMORY DEVICE FOR SIGNED MULTI-BIT TO MULTI-BIT MULTIPLICATIONS 审中-公开

    公开(公告)号：US20240304254A1

    公开(公告)日：2024-09-12

    申请号：US18423178

    申请日：2024-01-25

    Applicant: Micron Technology, Inc.

    Inventor： Hernan Castro

    IPC: G11C16/10 ,  G06F7/544 ,  G11C16/04

    CPC classification number: G11C16/102 ,  G06F7/5443 ,  G11C16/0433

    Abstract: Systems, methods, and apparatus related to memory devices that perform signed multi-bit to multi-bit multiplication using sets of memory cells. In one approach, a memory cell array has sets of memory cells. Each set is programmable to store a multi-bit signed weight. Voltage drivers apply voltages to each set. The voltages correspond to multi-bit signed inputs. One or more common lines are coupled to each set for summing output currents from the sets during the multiplication. A digitizer provides signed results based on summing the output currents. The signed results are added with adjustment for the bit significance of each signed result to provide a final accumulation result for the multiplication.

    MEMORY DEVICE PERFORMING SIGNED MULTIPLICATION USING SETS OF FOUR MEMORY CELLS
    18.
    发明公开
    MEMORY DEVICE PERFORMING SIGNED MULTIPLICATION USING SETS OF FOUR MEMORY CELLS 审中-公开

    公开(公告)号：US20240303038A1

    公开(公告)日：2024-09-12

    申请号：US18423168

    申请日：2024-01-25

    Applicant: Micron Technology, Inc.

    Inventor： Hernan Castro

    IPC: G06F7/523

    CPC classification number: G06F7/523

    Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using sets of four memory cells. In one approach, memory cells in a memory cell array are programmed so that each set stores a signed weight. Voltages are applied to the sets of memory cells. The voltages represent signed inputs to be multiplied by the signed weights. Output currents from the memory cells in each set are summed in first and second lines. A sum of the output currents in each line is digitized to provide first and second results. The first and second results are combined to provide a signed result for each set.

    MEMORY DEVICE HAVING BONDED INTEGRATED CIRCUIT DIES USED FOR MULTIPLICATION
    19.
    发明公开
    MEMORY DEVICE HAVING BONDED INTEGRATED CIRCUIT DIES USED FOR MULTIPLICATION 审中-公开

    公开(公告)号：US20240303037A1

    公开(公告)日：2024-09-12

    申请号：US18423151

    申请日：2024-01-25

    Applicant: Micron Technology, Inc.

    Inventor： Hernan Castro

    IPC: G06F7/523

    CPC classification number: G06F7/523

    Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells. In one approach, a first integrated circuit die has a memory cell array. The memory cell array includes memory cells programmable to store weights (e.g., representing synapses of a neural network). A second integrated circuit die has logic circuitry that performs multiplication of the stored weights by an input pattern. The second die is connected to the first die by hybrid bonding. Multiplication results are determined by the logic circuitry based on accumulation of output currents from at least a portion of the memory cells.

    MEMORY DEVICE PERFORMING MULTIPLICATION USING LOGICAL STATES OF MEMORY CELLS
    20.
    发明公开
    MEMORY DEVICE PERFORMING MULTIPLICATION USING LOGICAL STATES OF MEMORY CELLS 审中-公开

    公开(公告)号：US20240177772A1

    公开(公告)日：2024-05-30

    申请号：US18494652

    申请日：2023-10-25

    Applicant: Micron Technology, Inc.

    Inventor： Hernan Castro

    IPC: G11C13/00 ,  G06F7/544 ,  G11C19/36

    CPC classification number: G11C13/0069 ,  G06F7/5443 ,  G11C19/36

    Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using logical states of memory cells. In one approach, a memory cell array has memory cells programmed to store weights for performing the multiplication. Voltages are applied to the memory cells. Each voltage represents one or more input bits to be multiplied by one of the weights. Output currents from the memory cells are accumulated in a common bitline. A sum of the output currents is digitized to provide a digital result. The digital results from several bitlines can be shifted based on bit significance and added to provide a final accumulation result from the multiplication.

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