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公开(公告)号：US20250014648A1
公开(公告)日：2025-01-09
申请号：US18733520
申请日：2024-06-04
Applicant: Micron Technology, Inc.
Inventor： Jeremy M. Hirst , Hernan Castro
Abstract: Systems, methods, and apparatus related to memory devices that use multi-pillar memory cells for performing multiplication and other operations. In one approach, a memory cell array has memory cells used to perform matrix vector multiplication based on summing output currents from the memory cells. The memory cells are arranged in pillars of memory cells connected in series. Each memory cell uses at least one transistor from two or more different pillars. A bitline is formed overlying the pillars. The bitline is electrically connected to the pillars and accumulates output currents from the pillars when performing the matrix vector multiplication.
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2.发明公开公开(公告)号：US20240304255A1
公开(公告)日：2024-09-12
申请号：US18423181
申请日：2024-01-25
Applicant: Micron Technology, Inc.
Inventor： Hernan Castro
CPC classification number: G11C16/102 , G11C16/0433 , G11C16/08
Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells programmed to have different thresholds based on bit significance. In one approach, a memory cell array has memory cells that are each programmed to store one bit of a multi-bit weight. Voltage drivers apply voltages to the memory cells. The applied voltages represent inputs to be multiplied by the weights. A common line is coupled each of the memory cells to accumulate output currents from the cells. The output currents each have a magnitude corresponding to the significance of the bit stored by the respective memory cell. A digitizer uses the summed output currents as an input and provides a digital result as an output.
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公开(公告)号：US20200323083A1
公开(公告)日：2020-10-08
申请号：US16905363
申请日：2020-06-18
Applicant: Micron Technology, Inc.
Inventor： Hernan Castro , Stephen W. Russell , Stephen H. Tang
Abstract: Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.
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公开(公告)号：US20150074326A1
公开(公告)日：2015-03-12
申请号：US14023112
申请日：2013-09-10
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Hernan Castro
CPC classification number: G11C13/003 , G06F3/061 , G06F3/0658 , G06F3/0673 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0088 , G11C2213/15 , G11C2213/71 , G11C2213/77
Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.
Abstract translation: 用于在交叉点阵列中并行访问存储器单元的方法和结构包括并行地访问设置在第一选定列和第一选定行之间的第一存储器单元和布置在与第一选定列不同的第二选定列之间的第二存储单元 列和与第一选定行不同的第二选定行。 并行访问包括同时在第一所选列和第一选定行之间以及在第二选定列与第二选定行之间应用访问偏移。 在小区处于阈值状态或小区处于阈值后恢复周期时，并行进行访问。
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公开(公告)号：US08953387B2
公开(公告)日：2015-02-10
申请号：US13914170
申请日：2013-06-10
Applicant: Micron Technology, Inc.
Inventor： Hernan Castro
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0097 , G11C2013/0092 , G11C2213/77
Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.
Abstract translation: 包括存储器阵列（诸如交叉点阵列）的存储器电路可以包括可以同时用作选择元件/驱动器和去选择元件/驱动器的电路元件。 选择/取消选择驱动器可以用于提供选择功能以及操作功能。 操作功能可以包括为存储器阵列中的写入和/或读取操作提供足够的电流和电压。 当选择路径用于提供操作功能时，可以实现高效的交叉点实现。 操作功能可以通过去选择电源和/或去选择元件的电路操作来实现。
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Patent Agency Ranking
公开(公告)号：US20250072118A1
公开(公告)日：2025-02-27
申请号：US18826246
申请日：2024-09-06
Applicant: Micron Technology, Inc.
Inventor： Hernan Castro , Stephen W. Russell , Stephen H. Tang
Abstract: Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.
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公开(公告)号：US20250029659A1
公开(公告)日：2025-01-23
申请号：US18741633
申请日：2024-06-12
Applicant: Micron Technology, Inc.
Inventor： Kamal Karda , Hernan Castro
Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells. In one approach, a memory cell array has memory cells stacked vertically above a semiconductor substrate. Each memory cell stores a weight. Local digit lines connect to terminals of the memory cells. The local digit lines extend vertically above the substrate. Select transistors connect to the local digit lines. Select lines control the select transistors, and are used to encode an input pattern to multiply by the stored weights. Accumulation circuitry sums output currents from the memory cells. In one example, each memory cell is formed using a transistor that includes a semiconductor layer to provide a horizontal channel. A gate layer (e.g., a gate stack layer) wraps around a circumference of the semiconductor layer. Wordlines apply gate voltages to the transistors. Each wordline has a respective portion that wraps around a circumference of the gate layer of each transistor.
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公开(公告)号：US20240304253A1
公开(公告)日：2024-09-12
申请号：US18423174
申请日：2024-01-25
Applicant: Micron Technology, Inc.
Inventor： Hernan Castro
CPC classification number: G11C16/102 , G11C16/0433 , G11C16/26
Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using sets of memory cells. In one approach, memory cells in the sets are programmed so that each set stores a signed weight. Voltage drivers apply voltages to the memory cells in each set. The voltages correspond to signed inputs to multiply by the signed weights in the sets. One or more common lines (e.g., bitlines) are coupled to each set for summing output currents from the sets. A digitizer provides a signed result based on summing the output currents from the sets.
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公开(公告)号：US09230643B2
公开(公告)日：2016-01-05
申请号：US14528976
申请日：2014-10-30
Applicant: Micron Technology, Inc.
Inventor： Hernan Castro , Timothy C. Langtry , Richard Dodge , Ilya Karpov
CPC classification number: G11C13/004 , G11C13/0004 , G11C13/0061 , G11C13/0064 , G11C2013/0052
Abstract: Embodiments disclosed herein may relate to applying verify or read pulses for phase change memory and switch (PCMS) devices. The read pulses may be applied at a first voltage for a first period of time. A threshold event for the phase change memory cell may be detected during a sense window. The sense window may close after the expiration of the first period of time for which the read pulses are applied.
Abstract translation: 本文公开的实施例可以涉及为相变存储器和开关（PCMS）装置应用验证或读取脉冲。 读取脉冲可以以第一电压施加第一时间段。 可以在感测窗口期间检测相变存储器单元的阈值事件。 感应窗口可以在施加读取脉冲的第一时间段期满之后关闭。
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公开(公告)号：US20240304252A1
公开(公告)日：2024-09-12
申请号：US18423161
申请日：2024-01-25
Applicant: Micron Technology, Inc.
Inventor： Hernan Castro
CPC classification number: G11C16/102 , G11C16/24 , G11C16/26
Abstract: Systems, methods, and apparatus related to memory devices that perform signed multiplication using logical states of memory cells. In one approach, a memory device has a memory array including sets of memory cells programmed to store a signed weight in each set (e.g., four cells in a set store a signed weight of +1, 0, or −1). Voltages that represent signed inputs (e.g., +1, 0, or −1) are applied to the memory cells to perform the multiplication. A result from the multiplication is determined based on summing of output currents from the memory cells.
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