公开(公告)号：US20190097848A1

公开(公告)日：2019-03-28

申请号：US15716162

申请日：2017-09-26

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Raghukiran Sreeramaneni

IPC: H04L25/03 ,  H04L25/06

Abstract: A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.

公开(公告)号：US10147466B1

公开(公告)日：2018-12-04

申请号：US15716132

申请日：2017-09-26

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Raghukiran Sreeramaneni

IPC: G11C7/10 ,  G11C7/02 ,  G11C7/20

Abstract: A device includes a combinational circuit configured to create a one or more distortion correction factors used offset inter-symbol interference from a data stream on a distorted bit. The device also includes a selection circuit coupled o the combinational circuit. The selection circuit includes a feedback pin configured to receive a control signal and an output, wherein the selection circuit is configured to select a first distortion correction factor of the one or more distortion correction factors based upon the control signal and transmit the first distortion correction factor from the output.

公开(公告)号：US11908509B2

公开(公告)日：2024-02-20

申请号：US17701950

申请日：2022-03-23

Applicant: Micron Technology, Inc.

Inventor： John E. Riley ,  Scott E. Smith ,  Jennifer E. Taylor ,  Gary L. Howe

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C11/4096

Abstract: Methods, apparatuses, and systems related to operations for managing the quality of an input signal received by a device and for providing feedback in real-time. A controller can provide a reference signal to the device for the input quality check. The memory can implement the input quality check by counting the number of transitions of the reference signal for a set time period and store the resulting count value(s). The memory can use the count value(s) to determine a condition or a quality for the reference signal.

公开(公告)号：US11153132B2

公开(公告)日：2021-10-19

申请号：US16878288

申请日：2020-05-19

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Raghukiran Sreeramaneni

IPC: H04L25/03 ,  G11C7/10 ,  G11C11/401

Abstract: A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.

公开(公告)号：US20200126602A1

公开(公告)日：2020-04-23

申请号：US16723570

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Raghukiran Sreeramaneni ,  Jennifer E. Taylor

IPC: G11C7/10 ,  G11C29/02 ,  G11C7/22 ,  G11C29/52

Abstract: A device includes a signal input to receive a data input as part of a bit stream. The device also includes a reference input to receive a reference signal. The device further includes push circuitry to receive a first weight value, receive a first correction value, and generate a push signal based on the first weight value and the first correction value to selectively modify the data input as well as pull circuitry to receive a second weight value, receive a second correction value, and generate a pull signal based on the second weight value and the second correction value to selectively modify the data input.

公开(公告)号：US10482932B2

公开(公告)日：2019-11-19

申请号：US16204716

申请日：2018-11-29

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Raghukiran Sreeramaneni

IPC: G11C7/02 ,  G11C7/20 ,  G11C7/10

Abstract: A device includes a combinational circuit configured to create a one or more distortion correction factors used offset inter-symbol interference from a data stream on a distorted bit. The device also includes a selection circuit coupled to the combinational circuit. The selection circuit includes a feedback pin configured to receive a control signal and an output, wherein the selection circuit is configured to select a first distortion correction factor of the one or more distortion correction factors based upon the control signal and transmit the first distortion correction factor from the output.

公开(公告)号：US20190341089A1

公开(公告)日：2019-11-07

申请号：US16517165

申请日：2019-07-19

Applicant: Micron Technology, Inc.

Inventor： Raghukiran Sreeramaneni ,  Jennifer E. Taylor

IPC: G11C7/10 ,  G11C7/22

Abstract: A device includes a signal input to receive a data input as part of a bit stream. The device also includes a reference input to receive a reference signal. The device further includes push circuitry to receive a first weight value, receive a first correction value, and generate a push signal based on the first weight value and the first correction value to selectively modify the data input as well as pull circuitry to receive a second weight value, receive a second correction value, and generate a pull signal based on the second weight value and the second correction value to selectively modify the data input.

公开(公告)号：US20190222444A1

公开(公告)日：2019-07-18

申请号：US15872124

申请日：2018-01-16

Applicant: Micron Technology, Inc.

Inventor： Raghukiran Sreeramaneni ,  Jennifer E. Taylor

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03343 ,  H04L2025/03363

Abstract: A device includes a first bias level generator to generate a first bias level of a plurality of bias levels and transmit the bias level having a first voltage value, a second bias level generator to generate a second bias level of the plurality of bias levels and transmit the second bias level having a second voltage value. The device also includes a voltage divider that interpolates a subset of bias levels of the plurality of bias levels between the first bias level and the second bias level and supplies a selected bias level of the plurality of bias levels a control signal to an adjustment circuit of a decision feedback equalizer to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.

公开(公告)号：US20190198068A1

公开(公告)日：2019-06-27

申请号：US15850965

申请日：2017-12-21

Applicant: Micron Technology, Inc.

Inventor： Raghukiran Sreeramaneni ,  Jennifer E. Taylor

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1078 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/222

Abstract: A device includes a signal input to receive a data input as part of a bit stream. The device also includes a reference input to receive a reference signal. The device further includes push circuitry to receive a first weight value, receive a first correction value, and generate a push signal based on the first weight value and the first correction value to selectively modify the data input as well as pull circuitry to receive a second weight value, receive a second correction value, and generate a pull signal based on the second weight value and the second correction value to selectively modify the data input.

公开(公告)号：US10291439B1

公开(公告)日：2019-05-14

申请号：US15841144

申请日：2017-12-13

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Raghukiran Sreeramaneni

IPC: H04L25/03 ,  G11C11/401

Abstract: A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.