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公开(公告)号：US20210090680A1
公开(公告)日：2021-03-25
申请号：US16580935
申请日：2019-09-24
Applicant: Micron Technology, Inc.
Inventor： Shashank Bangalore Lakshman , Jonathan D. Harms , Jonathan J. Strand , Sukneet Singh Basuta
Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
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公开(公告)号：US20210090641A1
公开(公告)日：2021-03-25
申请号：US16581005
申请日：2019-09-24
Applicant: Micron Technology, Inc.
Inventor： Jonathan J. Strand , Sukneet Singh Basuta , Shashank Bangalore Lakshman , Jonathan D. Harms
Abstract: Methods, systems, and devices for imprint recovery for memory arrays are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
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公开(公告)号：US20250054560A1
公开(公告)日：2025-02-13
申请号：US18750246
申请日：2024-06-21
Applicant: Micron Technology, Inc.
Inventor： Jonathan D. Harms , Jonathan J. Strand , Sukneet Singh Basuta , Shashank Bangalore Lakshman
Abstract: Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
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公开(公告)号：US12019506B2
公开(公告)日：2024-06-25
申请号：US16581045
申请日：2019-09-24
Applicant: Micron Technology, Inc.
Inventor： Sukneet Singh Basuta , Shashank Bangalore Lakshman , Jonathan D. Harms , Jonathan J. Strand
CPC classification number: G06F11/0793 , G06F11/0727 , G06F11/0751 , G06F11/1068 , G06F12/10 , G11C11/221 , G11C11/2253 , G11C11/2273 , G11C11/2275
Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
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公开(公告)号：US11631473B2
公开(公告)日：2023-04-18
申请号：US17399872
申请日：2021-08-11
Applicant: Micron Technology, Inc.
Inventor： Shashank Bangalore Lakshman , Jonathan D. Harms , Jonathan J. Strand , Sukneet Singh Basuta
Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
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Patent Agency Ranking
公开(公告)号：US20230114735A1
公开(公告)日：2023-04-13
申请号：US18053305
申请日：2022-11-07
Applicant: Micron Technology, Inc.
Inventor： Angelo Visconti , Riccardo Pazzocco , Jonathan J. Strand , Kevin T. Majerus
Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.
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公开(公告)号：US11514968B2
公开(公告)日：2022-11-29
申请号：US16831524
申请日：2020-03-26
Applicant: Micron Technology, Inc.
Inventor： Angelo Visconti , Riccardo Pazzocco , Jonathan J. Strand , Kevin T. Majerus
Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.
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公开(公告)号：US11094394B2
公开(公告)日：2021-08-17
申请号：US16580935
申请日：2019-09-24
Applicant: Micron Technology, Inc.
Inventor： Shashank Bangalore Lakshman , Jonathan D. Harms , Jonathan J. Strand , Sukneet Singh Basuta
Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
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公开(公告)号：US20210089385A1
公开(公告)日：2021-03-25
申请号：US16581045
申请日：2019-09-24
Applicant: Micron Technology, Inc.
Inventor： Sukneet Singh Basuta , Shashank Bangalore Lakshman , Jonathan D. Harms , Jonathan J. Strand
Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
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20.发明授权公开(公告)号：US12266394B2
公开(公告)日：2025-04-01
申请号：US17831368
申请日：2022-06-02
Applicant: Micron Technology, Inc.
Inventor： Angelo Visconti , Jonathan J. Strand
IPC: G11C11/22
Abstract: Methods, systems, and devices for robust functionality for memory management associated with high-temperature storage are described. A memory device may apply a pattern (e.g., an imprint conditioning or deletion pattern) to at least a portion of memory cells of a memory array associated with a memory device before or after a power state procedure. The memory device may determine the pattern from various possible patterns, where the pattern may indicate a data state for each memory cell of the portion of memory cells. The pattern may indicate a same data state for each memory cell, an alternating data state for each memory cell, or an asymmetric switching pattern over a plurality of cycles, or any combination thereof. The memory device may write a respective logic value to at least some of the one or more memory cells of the portion of memory cells according to the pattern.
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