公开(公告)号：US20230297501A1

公开(公告)日：2023-09-21

申请号：US17262476

申请日：2020-12-07

Applicant: Micron Technology, Inc.

Inventor： Junjun Wang ,  Yi Heng Sun

IPC: G06F12/02 ,  G06F12/06

CPC classification number: G06F12/0253 ,  G06F12/0238 ,  G06F12/0653

Abstract: Methods, systems, and devices for techniques for accessing managed not-AND (NAND) memory are described. An indicator of a first type that indicates whether each physical address in a group of physical addresses stores valid data may be accessed. Indicators of a second type may be used to indicate whether respective physical addresses of the group of physical addresses store valid data. Data stored at the group of physical addresses may be transferred to a different group of physical addresses based on the indicator of the first type. Also, another indicator of the first type that indicates whether each physical address in the different group of physical addresses stores valid data may be updated.

公开(公告)号：US12204442B2

公开(公告)日：2025-01-21

申请号：US17414299

申请日：2021-04-27

Applicant: Micron Technology, Inc.

Inventor： Hua Tan ,  Junjun Wang ,  De Hua Guo

IPC: G11C16/04 ,  G06F12/02

Abstract: Methods, systems, and devices for dynamic voltage supply for memory circuit are described. An apparatus may adjust a supply voltage based on a process corner and a temperature of the memory system. An apparatus may include a memory array and a controller. The controller may determine a first temperature of the apparatus is less than a first temperature threshold at a first time. The controller may transition a voltage supplied to the controller from a first voltage level to a second voltage level based on determining the first temperature is less than the first temperature threshold. The controller may determine a second temperature is greater than a second temperature threshold at a second time. The controller may transition the voltage supplied to the controller from the second voltage level to the first voltage level based on determining the second temperature is greater than the second temperature threshold.

公开(公告)号：US12101183B2

公开(公告)日：2024-09-24

申请号：US17815912

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Zhanqiang Su ,  Junjun Wang

IPC: H04L1/00 ,  H04L1/1812 ,  H04L1/20

CPC classification number: H04L1/0061 ,  H04L1/1819 ,  H04L1/203

Abstract: Methods, systems, and devices for enhanced negative acknowledgment control (NAC) frame are described. A device may generate and communicate an enhanced NAC frame that includes additional error information to indicate to the device a cause for the error. The device may receive a data frame and determine an error condition associated with a set of layers of a protocol stack. The device may generate feedback indicating a cause for the determined error condition and transmit the feedback indicating the error cause. The feedback may be a NAC that includes a first quantity of bits configured for indicating an existence of an error and a second quantity of bits configured for indicating the error cause. A format of the NAC frame may include bits configured to identify multiple types of error causes associated with the different layers of the protocol stack.

公开(公告)号：US20240297928A1

公开(公告)日：2024-09-05

申请号：US18590755

申请日：2024-02-28

Applicant: Micron Technology, Inc.

Inventor： Junjun Wang ,  Zhanqiang Su

IPC: H04L69/40 ,  G06F11/14 ,  H04L69/323 ,  H04L69/324

CPC classification number: H04L69/40 ,  G06F11/1441 ,  H04L69/323 ,  H04L69/324

Abstract: Methods, systems, and devices for reset techniques for protocol layers of a memory system are described. A communications link may be established between a host system and the memory system. In some examples, the communications link may be based on one or more first parameters associated with a first protocol layer and one or more second parameters associated with a second protocol layer. The system may support communication (e.g., from the host system to the memory system) of an indication to reset the communications link, and the host system, the memory system, or both may reset the one or more first parameters based on communicating the indication to reset the communications link. The host system and memory system may attempt to reestablish the communications link based on resetting the one or more first parameters and maintaining the one or more second parameters.

公开(公告)号：US20240126685A1

公开(公告)日：2024-04-18

申请号：US17414299

申请日：2021-04-27

Applicant: Micron Technology, Inc.

Inventor： Hua Tan ,  Junjun Wang ,  De Hua Guo

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: Methods, systems, and devices for dynamic voltage supply for memory circuit are described. An apparatus may adjust a supply voltage based on a process corner and a temperature of the memory system. An apparatus may include a memory array and a controller. The controller may determine a first temperature of the apparatus is less than a first temperature threshold at a first time. The controller may transition a voltage supplied to the controller from a first voltage level to a second voltage level based on determining the first temperature is less than the first temperature threshold. The controller may determine a second temperature is greater than a second temperature threshold at a second time. The controller may transition the voltage supplied to the controller from the second voltage level to the first voltage level based on determining the second temperature is greater than the second temperature threshold.

公开(公告)号：US11886266B2

公开(公告)日：2024-01-30

申请号：US17736886

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Junjun Wang ,  Yanming Liu ,  Deping He ,  Hua Tan

IPC: G06F1/00 ,  G06F1/3225 ,  G06F1/3296 ,  G06F3/06 ,  G06F1/3203

CPC classification number: G06F1/3225 ,  G06F1/3296 ,  G06F3/0625 ,  G06F3/0659 ,  G06F1/3203 ,  G06F3/0679

Abstract: Methods, systems, and devices for dynamic power control are described. In some examples, a memory device may be configured to adjust a first duration for transitioning power modes. For example, the memory device may be configured to operate in a first power mode, a second power mode, and a third power mode. When operating in a second power mode, the memory device may be configured to increase or decrease the first duration for transitioning to a third power mode based on a second duration between received commands. If no commands are received during the first duration, the memory device may transition from the second power mode to the third power mode.

公开(公告)号：US20230342077A1

公开(公告)日：2023-10-26

申请号：US17050334

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Huachen Li ,  Xu Zhang ,  Xing Wang ,  Guan Zhong Wang ,  Tian Liang ,  Junjun Wang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0607 ,  G06F3/0658 ,  G06F3/0688

Abstract: Methods, systems, and devices for unmap backlog in a memory system are described. A memory system may be configured to support receiving an unmap command from a host system and signaling, to the host system, an indication that the unmap command has been processed (e.g., handled, acknowledged). In response to the unmap command, the memory system may proceed with various unmap operations, which may include unmapping at least some of the associated addresses after indicating that the unmap command has been processed. For example, a memory system may implement an unmap backlog table to identify sections of addresses that are to be unmapped (e.g., after indicating that the unmap command has been processed). In some examples, the memory system may support various aspects of prioritization between unmap operations (e.g., background unmap operations) and other access operations such as read operations, write operations, or other access operations.

公开(公告)号：US20230195646A1

公开(公告)日：2023-06-22

申请号：US17645686

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Yanming Liu ,  Zhenzhen Yang ,  Yi Heng Sun ,  Junjun Wang

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/657

Abstract: Methods, systems, and devices for flexible information compression at a memory system are described. For example, a memory system may compress information in a change log to reduce the frequency of transfers of one or more mappings between volatile memory and non-volatile memory. The memory system may compress information associated with a sequence of sequentially-indexed addresses by storing the information associated with those addresses at a pair of entries in the change log. The memory system may additionally switch between a first operating mode associated with identifying sequentially-indexed addresses and generating compressed entries, and a second operating mode associated with generating entries of the change log for each address received in commands.