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    APPARATUSES AND METHODS FOR FORCING MEMORY CELL FAILURES IN A MEMORY DEVICE
    12.
    发明申请
    APPARATUSES AND METHODS FOR FORCING MEMORY CELL FAILURES IN A MEMORY DEVICE 有权

    公开(公告)号：US20240395349A1

    公开(公告)日：2024-11-28

    申请号：US18667358

    申请日：2024-05-17

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yoshinori Fujiwara ,  Kenji Yoshida

    IPC: G11C29/46 ,  G11C29/00 ,  G11C29/24

    Abstract: Apparatuses and methods for forcing memory cell failures in a memory device are disclosed. An example apparatus includes a column disable control circuit coupled to a plurality of column latch sets to receive match signals and associated column plane addresses, the column disable control circuit configured to provide redundant column select signals and column plane masking signals based on the match signals and associated column plane addresses, the column disable control circuit further configured to provide the redundant column select signal and the column plane masking signal corresponding to an active match signal and associated column plane address from a designated column latch set when a disable memory test mode is enabled to cause one or more memory cells of main memory to fail.

    SEMICONDUCTOR DEVICE
    13.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180240511A1

    公开(公告)日：2018-08-23

    申请号：US15962886

    申请日：2018-04-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kenji Yoshida ,  Hiroki Fujisawa

    IPC: G11C11/406 ,  G11C11/4094

    CPC classification number: G11C11/40626 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094 ,  G11C2211/4061

    Abstract: Apparatuses and methods for refreshing memory cells of a semiconductor device are described. An example apparatus includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.

    SEMICONDUCTOR DEVICE INCLUDING FUSE CIRCUIT
    16.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING FUSE CIRCUIT 有权
    包括保险丝电路的半导体器件

    公开(公告)号：US20150255169A1

    公开(公告)日：2015-09-10

    申请号：US14635894

    申请日：2015-03-02

    Applicant: Micron Technology, Inc.

    Inventor： YUSUKE SAKAMOTO ,  Kenji Yoshida

    IPC: G11C17/16 ,  H03K19/177

    CPC classification number: G11C17/16 ,  G11C17/18 ,  G11C29/789 ,  H03K19/17768

    Abstract: Disclosed herein is an apparatus that includes a fuse circuit including a fuse element, the fuse circuit configured to provide a first output signal having a first voltage or a second voltage responsive to a state of the fuse element, and a sense circuit configured to provide a second output signal having the first voltage or a third voltage responsive to the first output signal, the third voltage different from the second voltage.

    Abstract translation: 本文公开了一种包括熔丝电路的装置，熔丝电路包括熔丝元件，熔丝电路被配置为提供响应于熔丝元件的状态的具有第一电压或第二电压的第一输出信号;以及感测电路， 第二输出信号具有响应于第一输出信号的第一电压或第三电压，第三电压不同于第二电压。

    SEMICONDUCTOR DEVICE
    17.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150036445A1

    公开(公告)日：2015-02-05

    申请号：US14447287

    申请日：2014-07-30

    Applicant: Micron Technology. Inc.

    Inventor： Kenji Yoshida ,  Hiroki Fujisawa

    IPC: G11C11/406

    CPC classification number: G11C11/40626 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094 ,  G11C2211/4061

    Abstract: Disclosed herein is a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.

    Abstract translation: 本文公开了一种半导体器件，其包括：存储单元阵列，包括多个存储器组，每个存储器组具有多个存储器单元，所述存储器组由相互不同的地址选择; 第一控制电路响应于第一刷新命令周期性地对存储器组执行刷新操作; 以及第二控制电路，其设定由第一控制电路执行刷新操作的循环。 第二控制电路将周期设置为第一周期，直到在接收到第一刷新命令之后对所有存储器组执行刷新操作，并且第二控制电路将该周期设置为比执行第一刷新命令之后的第一周期长的第二周期 刷新所有内存组的操作。

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