-
公开(公告)号：US20210134350A1
公开(公告)日：2021-05-06
申请号：US17147976
申请日：2021-01-13
Applicant: Micron Technology, Inc.
Inventor： Minoru Someya , Yukihide Suzuki , Sadayuki Okuma
IPC: G11C11/408 , G11C11/409 , G11C11/4074 , G11C7/10 , G11C7/22
Abstract: Compensating for offsets in buffers and related systems, methods, and devices are disclosed. An apparatus includes buffers, control circuitry, and fuses. Each of the buffers includes an output and an offset adjustment input. Each of the buffers is controllable to adjust a direct current offset of an output voltage potential responsive to an offset adjustment code provided to the offset adjustment input. The control circuitry includes sets of offset latches. The offset adjustment input of each of the buffers is operably coupled to a different one of the sets of offset latches. Each set of offset latches is configured to provide the offset adjustment code to the offset adjustment input of a corresponding buffer. The fuses are configured to provide the offset adjustment code to each of a subset of the sets of offset latches.
-
公开(公告)号：US20210055981A1
公开(公告)日：2021-02-25
申请号：US16545721
申请日：2019-08-20
Applicant: Micron Technology, Inc.
Inventor： Daniel S. Miller , Kevin G. Werhane , Yoshinori Fujiwara , Christopher G. Wieduwilt , Jason M. Johnson , Minoru Someya
Abstract: An example fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast and to encode the first data set to provide first signature data. The fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast and to encode the second data set to provide second signature data. The fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.
-
公开(公告)号：US20180075920A1
公开(公告)日：2018-03-15
申请号：US15668586
申请日：2017-08-03
Applicant: Micron Technology, Inc.
Inventor： Yoshinori Fujiwara , Kenji Yoshida , Minoru Someya , Hiromasa Noda
CPC classification number: G11C17/16 , G11C17/18 , G11C29/76 , G11C29/78 , G11C29/785 , G11C29/789 , H05K999/99
Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.
-
公开(公告)号：US09666307B1
公开(公告)日：2017-05-30
申请号：US15265671
申请日：2016-09-14
Applicant: Micron Technology, Inc.
Inventor： Yoshinori Fujiwara , Kenji Yoshida , Minoru Someya , Hiromasa Noda
CPC classification number: G11C17/16 , G11C17/18 , G11C29/76 , G11C29/78 , G11C29/785 , G11C29/789
Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.
-
公开(公告)号：US11645134B2
公开(公告)日：2023-05-09
申请号：US16545721
申请日：2019-08-20
Applicant: Micron Technology, Inc.
Inventor： Daniel S. Miller , Kevin G. Werhane , Yoshinori Fujiwara , Christopher G. Wieduwilt , Jason M. Johnson , Minoru Someya
CPC classification number: G06F11/0751 , G06F11/0727 , G11C17/16 , H03K19/21
Abstract: An example fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast and to encode the first data set to provide first signature data. The fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast and to encode the second data set to provide second signature data. The fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.
-
Patent Agency Ranking
公开(公告)号：US11183260B1
公开(公告)日：2021-11-23
申请号：US17098865
申请日：2020-11-16
Applicant: Micron Technology, Inc.
Inventor： Yoshinori Fujiwara , Dave Jefferson , Jason M. Johnson , Vivek Kotti , Minoru Someya , Toru Ishikawa , Kevin G. Werhane
Abstract: Memory devices are disclosed. A memory device may include a number of fuses and a number of transmit lines configured to transmit data from the number of fuses. The memory device may also include a number of monitoring circuits. Each monitoring circuit of the number of monitoring circuits is coupled to a transmit line of the number of transmit lines. Each monitoring circuit comprises logic configured to receive the data from the number fuses via the transmit line. The logic is further configured to generate a result responsive to the data and indicative of pass/fail status of the transmit line. Associated methods and systems are also disclosed.
-
公开(公告)号：US09824770B1
公开(公告)日：2017-11-21
申请号：US15493772
申请日：2017-04-21
Applicant: Micron Technology, Inc.
Inventor： Yoshinori Fujiwara , Kenji Yoshida , Minoru Someya , Hiromasa Noda
CPC classification number: G11C17/16 , G11C17/18 , G11C29/76 , G11C29/78 , G11C29/785 , G11C29/789
Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.
-
公开(公告)号：US11749366B2
公开(公告)日：2023-09-05
申请号：US17578305
申请日：2022-01-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yasushi Matsubara , Alan Wilson , Minoru Someya
CPC classification number: G11C29/027 , G11C7/1012 , G11C8/18 , G11C29/1201 , G11C29/12015 , G11C29/18 , G11C29/4401
Abstract: Disclosed herein is an apparatus that includes a fuse array circuit including a plurality of fuse sets each assigned to a corresponding one of a plurality of fuse addresses and configured to operatively store a fuse data, and a first circuit configured to generate and sequentially update a fuse address to sequentially read the fuse data from the plurality of fuse sets. The first circuit is configured to change a frequency of updating the fuse address based on a first signal.
-
公开(公告)号：US20230230648A1
公开(公告)日：2023-07-20
申请号：US17578305
申请日：2022-01-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yasushi Matsubara , Alan Wilson , Minoru Someya
CPC classification number: G11C29/027 , G11C29/4401 , G11C29/1201 , G11C29/12015 , G11C29/18 , G11C8/18 , G11C7/1012
Abstract: Disclosed herein is an apparatus that includes a fuse array circuit including a plurality of fuse sets each assigned to a corresponding one of a plurality of fuse addresses and configured to operatively store a fuse data, and a first circuit configured to generate and sequentially update a fuse address to sequentially read the fuse data from the plurality of fuse sets. The first circuit is configured to change a frequency of updating the fuse address based on a first signal.
-
公开(公告)号：US11322194B2
公开(公告)日：2022-05-03
申请号：US17147976
申请日：2021-01-13
Applicant: Micron Technology, Inc.
Inventor： Minoru Someya , Yukihide Suzuki , Sadayuki Okuma
IPC: G11C8/00 , G11C11/408 , G11C11/409 , G11C7/10 , G11C7/22 , G11C11/4074
Abstract: Compensating for offsets in buffers and related systems, methods, and devices are disclosed. An apparatus includes buffers, control circuitry, and fuses. Each of the buffers includes an output and an offset adjustment input. Each of the buffers is controllable to adjust a direct current offset of an output voltage potential responsive to an offset adjustment code provided to the offset adjustment input. The control circuitry includes sets of offset latches. The offset adjustment input of each of the buffers is operably coupled to a different one of the sets of offset latches. Each set of offset latches is configured to provide the offset adjustment code to the offset adjustment input of a corresponding buffer. The fuses are configured to provide the offset adjustment code to each of a subset of the sets of offset latches.
-
-
-
-
-
-
-
-
-
Search Results
13
records
(took 0.015 seconds)
