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    LINK EVALUATION FOR A MEMORY DEVICE
    11.
    发明申请
    LINK EVALUATION FOR A MEMORY DEVICE 有权

    公开(公告)号：US20210193252A1

    公开(公告)日：2021-06-24

    申请号：US17121314

    申请日：2020-12-14

    Applicant: Micron Technology, Inc.

    Inventor： Markus Balb ,  Thomas Hein ,  Heinz Hoenigschmid

    IPC: G11C29/44 ,  G11C29/12 ,  G11C29/38

    Abstract: Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.

    Multi-level signaling in memory with wide system interface
    13.
    发明授权
    Multi-level signaling in memory with wide system interface 有权

    公开(公告)号：US12237953B2

    公开(公告)日：2025-02-25

    申请号：US17564867

    申请日：2021-12-29

    Applicant: Micron Technology, Inc.

    Inventor： Timothy M. Hollis ,  Markus Balb ,  Ralf Ebert

    IPC: H04L25/49 ,  G11C7/10

    Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

    Detection of illegal commands
    14.
    发明授权
    Detection of illegal commands 有权

    公开(公告)号：US11693602B2

    公开(公告)日：2023-07-04

    申请号：US17826994

    申请日：2022-05-27

    Applicant: Micron Technology, Inc.

    Inventor： Michael Dieter Richter ,  Markus Balb

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

    Abstract: Methods, systems, and devices for detection of illegal commands are described. A memory device, such as a dynamic random access memory (DRAM), may receive a command from a device, such as a host device, to perform an access operation on at least one memory cell of a memory device. The memory device may determine, using a detection component, that a timing threshold associated with an operation of the memory device would be violated by performing the access operation. The memory device may refrain from executing the access operation based on determining that performing the access operation included in the command would violate the timing threshold. The memory device may transmit, to the device, an indication that performing the command would violate the timing threshold.

    MULTI-LEVEL SIGNALING IN MEMORY WITH WIDE SYSTEM INTERFACE
    15.
    发明申请
    MULTI-LEVEL SIGNALING IN MEMORY WITH WIDE SYSTEM INTERFACE 有权

    公开(公告)号：US20220123974A1

    公开(公告)日：2022-04-21

    申请号：US17564867

    申请日：2021-12-29

    Applicant: Micron Technology, Inc.

    Inventor： Timothy M. Hollis ,  Markus Balb ,  Ralf Ebert

    IPC: H04L25/49 ,  G11C7/10

    Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

    Multi-level signaling in memory with wide system interface
    16.
    发明授权
    Multi-level signaling in memory with wide system interface 有权

    公开(公告)号：US11233681B2

    公开(公告)日：2022-01-25

    申请号：US16866191

    申请日：2020-05-04

    Applicant: Micron Technology, Inc.

    Inventor： Timothy M. Hollis ,  Markus Balb ,  Ralf Ebert

    IPC: H04L25/49 ,  G11C7/10

    Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

    INTERRUPT SIGNALING FOR A MEMORY DEVICE
    17.
    发明申请
    INTERRUPT SIGNALING FOR A MEMORY DEVICE 有权

    公开(公告)号：US20210181990A1

    公开(公告)日：2021-06-17

    申请号：US17116180

    申请日：2020-12-09

    Applicant: Micron Technology, Inc.

    Inventor： Markus Balb ,  Thomas Hein ,  Heinz Hoenigschmid

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for interrupt signaling for a memory device are described. A memory device may transmit an interrupt signal to a host device to alter a sequence of operations that would otherwise be executed by the host device. The memory device may transmit the interrupt signal in response to detecting an error condition at the memory device, a performance degradation at the memory device, or another trigger event. In some examples, the memory device may include a dedicated interrupt pin for transmitting interrupt signals. Alternatively, the memory device may transmit interrupt signals via a pin also sued to transmit error detection codes. For example, the memory device may transmit an interrupt signal before or after an error detection code or may invert the error detection code to indicate the interrupt, in which case the inverted error detection code may act as an interrupt signal.

    MULTI-LEVEL SIGNALING IN MEMORY WITH WIDE SYSTEM INTERFACE
    18.
    发明申请
    MULTI-LEVEL SIGNALING IN MEMORY WITH WIDE SYSTEM INTERFACE 审中-公开

    公开(公告)号：US20200267032A1

    公开(公告)日：2020-08-20

    申请号：US16866191

    申请日：2020-05-04

    Applicant: Micron Technology, Inc.

    Inventor： Timothy M. Hollis ,  Markus Balb ,  Ralf Ebert

    IPC: H04L25/49 ,  G11C7/10

    Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

    Multi-level signaling in memory with wide system interface
    19.
    发明授权
    Multi-level signaling in memory with wide system interface 有权

    公开(公告)号：US10686634B2

    公开(公告)日：2020-06-16

    申请号：US16536179

    申请日：2019-08-08

    Applicant: Micron Technology, Inc.

    Inventor： Timothy M. Hollis ,  Markus Balb ,  Ralf Ebert

    IPC: H04L25/49 ,  G11C7/10

    Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

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