公开(公告)号：US20230205615A1

公开(公告)日：2023-06-29

申请号：US18068152

申请日：2022-12-19

Applicant: Micron Technology, Inc.

Inventor： Melissa I. Uribe ,  Aaron P. Boehm

IPC: G06F11/07

CPC classification number: G06F11/0772 ,  G06F11/073 ,  G06F11/079

Abstract: Methods, systems, and devices for error detection signaling are described. In some examples, a memory device may include circuitry to detect one or more error conditions. As the memory device is operated, it may store or output a value (e.g., a high value, a “1”) indicating the absence of an error condition. Upon the occurrence of an error condition, the memory device may either store or output a value (e.g., a low value, a “0”), which may allow for the error to be corrected or mitigated. Because storing or driving the value signifying the error condition may require a driver of the memory device to be coupled with a power supply, storing or outputting the value signifying an absence of an error condition (e.g., unless a normal or valid condition is detected) may mitigate errors that would otherwise render a safety mechanism of the memory device ineffective.

公开(公告)号：US20250028597A1

公开(公告)日：2025-01-23

申请号：US18904612

申请日：2024-10-02

Applicant: Micron Technology, Inc.

Inventor： Melissa I. Uribe

IPC: G06F11/10

Abstract: Methods, systems, and devices for memory operations are described. A pin associated with communicating error correction information may be biased, via a first circuit, to a first voltage level by a first voltage source that is coupled with the pin when the pin is in an idle state. Also, a set of data pins may be biased, via a second circuit, to a second voltage level by a second voltage source when the set of data pins is in the idle state. When a memory device misses a command transmitted from a host device, the voltage levels of the pin and set of data pins may remain at the respective voltage levels throughout a period during which the host device executes an operation associated with the missed command, indicating to the host device that data communicated by a corresponding data signal is invalid.

公开(公告)号：US12130702B2

公开(公告)日：2024-10-29

申请号：US17880220

申请日：2022-08-03

Applicant: Micron Technology, Inc.

Inventor： Melissa I. Uribe

IPC: G06F11/10 ,  G06F11/00

CPC classification number: G06F11/1048 ,  G06F11/1076

Abstract: Methods, systems, and devices for memory operations are described. A pin associated with communicating error correction information may be biased, via a first circuit, to a first voltage level by a first voltage source that is coupled with the pin when the pin is in an idle state. Also, a set of data pins may be biased, via a second circuit, to a second voltage level by a second voltage source when the set of data pins is in the idle state. When a memory device misses a command transmitted from a host device, the voltage levels of the pin and set of data pins may remain at the respective voltage levels throughout a period during which the host device executes an operation associated with the missed command, indicating to the host device that data communicated by a corresponding data signal is invalid.

公开(公告)号：US20240161854A1

公开(公告)日：2024-05-16

申请号：US18423059

申请日：2024-01-25

Applicant: Micron Technology, Inc.

Inventor： Melissa I. Uribe

IPC: G11C29/42 ,  G11C7/10 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C7/1039 ,  G11C7/1069 ,  G11C7/1096 ,  G11C29/4401

Abstract: Methods, systems, and devices for read command fault detection in a memory system are described. For example, a memory device may be configured to set a field of a register with a first value, corresponding to a state where a read command has not been decoded. If the memory device receives and decodes a read command from a host device, the memory device may set the field with a second value. The memory device indicate a value of the field of the register to the host device, which may be used to evaluate whether to process information interpreted over an interface between the host device and the memory device. For example, if the host device receives an indication of the second value, the host device may proceed with processing and, if the host device receives an indication of the first value, the host device may refrain from processing.

公开(公告)号：US11923027B2

公开(公告)日：2024-03-05

申请号：US17646264

申请日：2021-12-28

Applicant: Micron Technology, Inc.

Inventor： Melissa I. Uribe

IPC: G11C29/42 ,  G11C7/10 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C7/1039 ,  G11C7/1069 ,  G11C7/1096 ,  G11C29/4401

Abstract: Methods, systems, and devices for read command fault detection in a memory system are described. For example, a memory device may be configured to set a field of a register with a first value, corresponding to a state where a read command has not been decoded. If the memory device receives and decodes a read command from a host device, the memory device may set the field with a second value. The memory device indicate a value of the field of the register to the host device, which may be used to evaluate whether to process information interpreted over an interface between the host device and the memory device. For example, if the host device receives an indication of the second value, the host device may proceed with processing and, if the host device receives an indication of the first value, the host device may refrain from processing.

公开(公告)号：US20230197180A1

公开(公告)日：2023-06-22

申请号：US18080369

申请日：2022-12-13

Applicant: Micron Technology, Inc.

Inventor： Steffen Buch ,  Melissa I. Uribe

IPC: G11C29/42

CPC classification number: G11C29/42 ,  G11C2211/5641

Abstract: Methods, systems, and devices for address fault detection are described. In some examples, a memory device may receive a command (e.g., a write command) and data, and may generate a set of parity bits based on an address of the command and the data. The data and the set of parity bits may be stored to respective portions of a memory array. In some examples, the memory device may receive a command (e.g., a read command) for the data. The memory device may read the data and may generate a set of parity bits (e.g., a second set of parity bits) based on an address of the command and the read data. The sets of parity bits may be compared to determine whether an error associated with the data exists, an error associated with an address path of the memory exists, or both.

公开(公告)号：US20250130878A1

公开(公告)日：2025-04-24

申请号：US18954300

申请日：2024-11-20

Applicant: Micron Technology, Inc.

Inventor： Melissa I. Uribe ,  Aaron P. Boehm

IPC: G06F11/07

Abstract: Methods, systems, and devices for error detection signaling are described. In some examples, a memory device may include circuitry to detect one or more error conditions. As the memory device is operated, it may store or output a value (e.g., a high value, a “1”) indicating the absence of an error condition. Upon the occurrence of an error condition, the memory device may either store or output a value (e.g., a low value, a “0”), which may allow for the error to be corrected or mitigated. Because storing or driving the value signifying the error condition may require a driver of the memory device to be coupled with a power supply, storing or outputting the value signifying an absence of an error condition (e.g., unless a normal or valid condition is detected) may mitigate errors that would otherwise render a safety mechanism of the memory device ineffective.

公开(公告)号：US12014787B2

公开(公告)日：2024-06-18

申请号：US17657063

申请日：2022-03-29

Applicant: Micron Technology, Inc.

Inventor： Melissa I. Uribe

IPC: G11C29/02 ,  G11C11/4076 ,  G11C11/4099 ,  H03K19/20

CPC classification number: G11C29/022 ,  G11C11/4076 ,  G11C11/4099 ,  G11C29/021 ,  H03K19/20

Abstract: Methods, systems, and devices for techniques for determining an interface connection status are described. A system may include an interface between a host device and a memory device. The host device may transmit to the memory device first data in a pattern over a first set of transmission lines of the interface. The host device may also transmit to the memory device second data in the pattern over a second set of transmission lines of the interface. The memory device may compare the first data and the second data, and based on the comparison, send an indication of a connection status of the interface to the host device.

公开(公告)号：US20230317191A1

公开(公告)日：2023-10-05

申请号：US17657063

申请日：2022-03-29

Applicant: Micron Technology, Inc.

Inventor： Melissa I. Uribe

IPC: G11C29/02 ,  G11C11/4076 ,  G11C11/4099 ,  H03K19/20

CPC classification number: G11C29/022 ,  G11C29/021 ,  G11C11/4076 ,  G11C11/4099 ,  H03K19/20

Abstract: Methods, systems, and devices for techniques for determining an interface connection status are described. A system may include an interface between a host device and a memory device. The host device may transmit to the memory device first data in a pattern over a first set of transmission lines of the interface. The host device may also transmit to the memory device second data in the pattern over a second set of transmission lines of the interface. The memory device may compare the first data and the second data, and based on the comparison, send an indication of a connection status of the interface to the host device.

公开(公告)号：US20230315564A1

公开(公告)日：2023-10-05

申请号：US17711002

申请日：2022-03-31

Applicant: Micron Technology, Inc.

Inventor： Melissa I. Uribe

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: A memory device is provided. The memory device includes a memory bank configured to store data in one or more memory cells. The memory device further includes an address fault detection system designed to detect a mismatch between the address originally used to store the data and the address subsequently used to read the data. The address fault detection system generates an address parity bit from the received address and either stores that address parity bit with the user data or uses the address parity bit to invert the internal ECC bits generated from the user data. The address fault detection system can determine from the resulting syndrome from the ECC bits whether or not an address fault has occurred and raise an address fault indication flag if the address fault is detected.