公开(公告)号：US10515972B2

公开(公告)日：2019-12-24

申请号：US15685878

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat ,  Luan C. Tran ,  Meng-Wei Kuo ,  Yushi Hu

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/822 ,  H01L27/11578 ,  H01L27/11529 ,  H01L27/1158

Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

公开(公告)号：US20160293623A1

公开(公告)日：2016-10-06

申请号：US14679926

申请日：2015-04-06

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Meng-Wei Kuo ,  John D. Hopkins

IPC: H01L27/115 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.

Abstract translation: 一些实施例包括形成垂直堆叠的存储单元的方法。 通过交替的绝缘和导电水平的叠层形成开口。 空穴形成为延伸到导电水平。 绝缘水平的区域保持为将相邻腔彼此分开的壁架。 将材料从凸缘上移除以使突出部分变薄，然后在腔内形成电荷阻挡电介质和电荷存储结构。 一些实施例包括具有交替绝缘水平和导电水平的叠层的集成结构。 穴位扩展到导电水平。 绝缘层的楔形物将相邻的空腔彼此分开。 相对于不包括在突出部分的绝缘水平的区域，这些壁架变薄。 电荷阻挡电介质和电荷存储结构在空腔内。