公开(公告)号：US20250159875A1

公开(公告)日：2025-05-15

申请号：US19022029

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran ,  Guangyu Huang ,  Haitao Liu

IPC: H10B41/27 ,  G11C5/06 ,  H10B41/35 ,  H10B41/60 ,  H10B43/27 ,  H10B43/35

Abstract: A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.

公开(公告)号：US11937423B2

公开(公告)日：2024-03-19

申请号：US17746649

申请日：2022-05-17

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran ,  Guangyu Huang ,  Haitao Liu

IPC: H10B41/27 ,  G11C5/06 ,  H10B41/35 ,  H10B41/60 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C5/063 ,  H10B41/35 ,  H10B41/60 ,  H10B43/27 ,  H10B43/35

Abstract: A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.

公开(公告)号：US20210272975A1

公开(公告)日：2021-09-02

申请号：US17322390

申请日：2021-05-17

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran

IPC: H01L27/11556 ,  H01L21/28 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/02 ,  H01L27/11524 ,  H01L29/423 ,  H01L29/788

Abstract: Disclosed are memory structures and methods for forming such structures. An example method forms a vertical string of memory cells by forming an opening in interleaved tiers of dielectric tier material and nitride tier material, forming a charge storage material over sidewalls of the opening and recesses in the opening to form respective charge storage structures within the recesses. Subsequently, and separate from the formation of the floating gate structures, at least a portion of the remaining nitride tier material is removed to produce control gate recesses, each adjacent a respective charge storage structure. A control gate is formed in each control gate recess, and the control gate is separated from the charge storage structure by a dielectric structure. In some examples, these dielectric structures are also formed separately from the charge storage structures.

公开(公告)号：US11011538B2

公开(公告)日：2021-05-18

申请号：US16406148

申请日：2019-05-08

Applicant: Micron Technology, inc.

Inventor： David H. Wells ,  Luan C. Tran ,  Jie Li ,  Anish A. Khandekar ,  Kunal Shrotri

IPC: H01L27/11582 ,  H01L29/51 ,  H01L29/10 ,  H01L29/06 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L21/28 ,  H01L21/02

Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.

公开(公告)号：US10297611B1

公开(公告)日：2019-05-21

申请号：US15903307

申请日：2018-02-23

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Luan C. Tran ,  Jie Li ,  Anish A. Khandekar ,  Kunal Shrotri

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/51 ,  H01L29/10 ,  H01L29/06 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L21/02

Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.

公开(公告)号：US20180211868A1

公开(公告)日：2018-07-26

申请号：US15925418

申请日：2018-03-19

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran

IPC: H01L21/768 ,  H01L27/11524 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11529 ,  H01L27/07 ,  H01L23/528 ,  H01L27/11546

CPC classification number: H01L21/76816 ,  H01L21/02518 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0705 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/40114 ,  H01L29/66477 ,  H01L29/66825 ,  H01L29/788

Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.

公开(公告)号：US20180069015A1

公开(公告)日：2018-03-08

申请号：US15808468

申请日：2017-11-09

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Lijing Gou ,  Gordon Haller ,  Luan C. Tran

IPC: H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L21/28035 ,  H01L21/28282 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/31105 ,  H01L21/32055 ,  H01L27/11582

Abstract: Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the SGD transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the SGD transistor. Additional apparatus and methods are disclosed.

公开(公告)号：US09780102B2

公开(公告)日：2017-10-03

申请号：US14536021

申请日：2014-11-07

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat ,  Luan C. Tran ,  Meng-Wei Kuo ,  Yushi Hu

IPC: H01L29/788 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/822 ,  H01L27/11578 ,  H01L27/11529 ,  H01L27/1158

CPC classification number: H01L27/11524 ,  H01L21/8221 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

公开(公告)号：US09666695B2

公开(公告)日：2017-05-30

申请号：US14592498

申请日：2015-01-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luan C. Tran

IPC: H01L29/66 ,  H01L21/033 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L21/02 ,  H01L29/788 ,  H01L21/28 ,  H01L27/11565 ,  H01L27/11568

CPC classification number: H01L21/76816 ,  H01L21/02518 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28273 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0705 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/66477 ,  H01L29/66825 ,  H01L29/788

Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.

公开(公告)号：US09437480B2

公开(公告)日：2016-09-06

申请号：US14662918

申请日：2015-03-19

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/314 ,  H01L21/316 ,  H01L23/48 ,  H01L21/308 ,  H01L27/108

CPC classification number: H01L21/76802 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/481 ,  H01L27/108 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.

Abstract translation: 制造具有与有源区域特征对准的紧密节距触点的半导体结构的方法，并且使用用于限定具有亚光刻尺寸的图案的各种技术同时制造自对准的紧密节距触点和导线。 还公开了具有与有源区域特征对准的紧密节距触点的半导体结构以及可选地对齐的导线，半导体结构具有紧密的节距接触孔和用于导线的对准的沟槽。