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    Integrated structures and methods of forming vertically-stacked memory cells
    3.
    发明授权
    Integrated structures and methods of forming vertically-stacked memory cells 有权

    公开(公告)号：US11482534B2

    公开(公告)日：2022-10-25

    申请号：US16861093

    申请日：2020-04-28

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Meng-Wei Kuo ,  John D. Hopkins

    IPC: H01L21/8239 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/1157

    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.

    MEMORY CELL PILLAR INCLUDING SOURCE JUNCTION PLUG
    4.
    发明申请
    MEMORY CELL PILLAR INCLUDING SOURCE JUNCTION PLUG 有权
    存储单元支柱，包括源结点插头

    公开(公告)号：US20160133638A1

    公开(公告)日：2016-05-12

    申请号：US14536021

    申请日：2014-11-07

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat ,  Luan C. Tran ,  Meng-Wei Kuo ,  Yushi Hu

    IPC: H01L27/115

    CPC classification number: H01L27/11524 ,  H01L21/8221 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/11582

    Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

    Abstract translation: 一些实施例包括具有源材料，源材料上方的介电材料，介电材料上方的选择栅极材料，选择栅极材料上方的存储单元堆叠，位于介电材料的开口中的导电插塞的装置和方法，以及 接触源材料的一部分，以及延伸穿过存储单元堆叠和选择栅极材料并与导电插塞接触的沟道材料。

    Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells
    6.
    发明申请
    Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells 审中-公开

    公开(公告)号：US20200258910A1

    公开(公告)日：2020-08-13

    申请号：US16861093

    申请日：2020-04-28

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Meng-Wei Kuo ,  John D. Hopkins

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/11556

    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.

    Integrated structures of vertically-stacked memory cells
    7.
    发明授权
    Integrated structures of vertically-stacked memory cells 审中-公开

    公开(公告)号：US10672785B2

    公开(公告)日：2020-06-02

    申请号：US14679926

    申请日：2015-04-06

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Meng-Wei Kuo ,  John D. Hopkins

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/1157

    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.

    BIT LINE CONTACT SCHEME IN A MEMORY SYSTEM STACK
    8.
    发明公开
    BIT LINE CONTACT SCHEME IN A MEMORY SYSTEM STACK 审中-公开

    公开(公告)号：US20240355363A1

    公开(公告)日：2024-10-24

    申请号：US18630919

    申请日：2024-04-09

    Applicant: Micron Technology, Inc.

    Inventor： Mithun Kumar Ramasahayam ,  Indra V. Chary ,  Meng-Wei Kuo

    IPC: G11C5/06 ,  G11C16/04 ,  H01L29/49 ,  H10B43/27 ,  H10B43/35

    CPC classification number: G11C5/063 ,  G11C16/0483 ,  H01L29/4966 ,  H10B43/27 ,  H10B43/35

    Abstract: Methods, systems, and devices for a bit line contact scheme in a memory system stack are described. A memory architecture may include bit lines coupled with bit line contacts, and pillars coupled with circuitry associated with supporting operation of the bit lines. Hybrid plugs may be integrated into the pillars to couple the bit line contacts with the pillars, forming a conductive path between the bit lines and the circuitry. The hybrid plugs may be recessed within the pillars such that the hybrid plugs do not extend through the memory architecture beyond the pillars. The hybrid plugs may include one or more relatively low capacitance, conductive materials, such as a titanium alloy material (e.g., titanium, titanium nitride), a tungsten alloy material (e.g., tungsten, tungsten nitride), or any combination thereof, among other materials.

    Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells
    10.
    发明申请
    Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells 有权

    公开(公告)号：US20230019097A1

    公开(公告)日：2023-01-19

    申请号：US17946837

    申请日：2022-09-16

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Meng-Wei Kuo ,  John D. Hopkins

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/8239

    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.

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