公开(公告)号：US10747693B2

公开(公告)日：2020-08-18

申请号：US15976726

申请日：2018-05-10

Applicant: Micron Technology, Inc.

Inventor： Michael V. Ho ,  Ravi Kiran Kandikonda

IPC: G06F13/16 ,  G06F13/20 ,  G06F3/06 ,  G11C11/4063 ,  G06F13/40

Abstract: A memory device includes a first set of data input/output (I/O) devices configured to communicate a first portion of a data unit to or from an external controller; a second set of data I/O devices configured to communicate a second portion of the data unit to or from the external controller; a data control circuit can share the internal global data lines by multiplexing the timings of the first and second sets of data I/O devices, the data control circuit configured to route the data unit according to a data operation corresponding to the data unit; and a shared data bus coupling both the first set of data I/O devices and the second set of data I/O devices to the data control circuit, the shared data bus configured to relay both the first portion and the second portion of the data unit.

公开(公告)号：US20200035290A1

公开(公告)日：2020-01-30

申请号：US16593675

申请日：2019-10-04

Applicant: Micron Technology, Inc.

Inventor： Michael V. Ho

IPC: G11C11/4076 ,  G11C7/22 ,  G11C11/4093 ,  G06F13/16

Abstract: A semiconductor device may include a number of memory banks, an output buffer that couples to the memory banks, a number of switches that couple a voltage source to the output buffer, and a stagger delay circuit. The stagger delay circuit may include a resistor-capacitor (RC) circuit that outputs a current signal that corresponds to a data voltage signal received by the RC circuit. The stagger delay circuit may also include a logic circuit that determines a strength of the current signal and sends a first gate signal to a first portion of the switches based on the strength.

公开(公告)号：US10366743B1

公开(公告)日：2019-07-30

申请号：US15976716

申请日：2018-05-10

Applicant: Micron Technology, Inc.

Inventor： Michael V. Ho ,  Byung S. Moon

IPC: G11C11/24 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/4076 ,  G11C11/4093

Abstract: Memory devices and systems in which array data lines of a local data bus are shared between two or more memory bank groups in a memory array. In one embodiment, a memory device is provided, comprising a memory array, I/O gating circuitry, and a local data bus. The local data bus can include a plurality of array data lines shared between two or more memory bank groups of the memory array. The local data bus can electrically couple and transfer data between the two or more memory bank groups and the I/O gating circuitry. In some embodiments, one or more data latches can be electrically coupled to the local data bus to (i) transfer data off the local data bus to free the plurality of data lines for subsequent data transfers and/or (ii) match varying data propagation timings on the local data with column generations of the memory bank groups.

公开(公告)号：US11158570B2

公开(公告)日：2021-10-26

申请号：US15976674

申请日：2018-05-10

Applicant: Micron Technology, Inc.

Inventor： Michael V. Ho ,  Eric J. Smith

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/02

Abstract: Semiconductor devices having busing layouts configured to reduce on-die capacitance are disclosed herein. In one embodiment, a semiconductor device includes an electrostatic discharge device electrically connected in parallel with an integrated circuit and configured to divert high voltages generated during an electrostatic discharge event away from the integrated circuit. The semiconductor device further includes a signal bus and a power bus electrically connected to the electrostatic discharge device. The signal bus includes a plurality of first fingers grouped into first groups and the power bus includes a plurality of second fingers grouped into second groups. The first groups are positioned generally parallel to and interleaved between the second groups.

公开(公告)号：US20210287731A1

公开(公告)日：2021-09-16

申请号：US16817095

申请日：2020-03-12

Applicant: Micron Technology, Inc.

Inventor： Younghoon Oh ,  Michael V. Ho

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C11/4093 ,  G11C7/10 ,  H03L7/081

Abstract: An apparatus includes a memory device interface comprising a first data output, a second data output, a third data output, and a fourth data output, as well as a first path corresponding to the first data output, a second path corresponding to the second data output, a third path corresponding to the third data output, and a fourth path corresponding to the fourth data output. The apparatus also includes a signal transmission circuit comprising a first output that when in operation transmits a first clock signal to the first path, the second path, the third path, and the fourth path and a second output that when in operation transmits a second clock signal to the first path, the second path, the third path, and the fourth path.

公开(公告)号：US10950291B1

公开(公告)日：2021-03-16

申请号：US16661784

申请日：2019-10-23

Applicant: Micron Technology, Inc.

Inventor： Michael V. Ho ,  Myung Ho Bae

IPC: G11C11/40 ,  G11C11/4076 ,  G11C11/4074 ,  G11C11/408 ,  H03K3/017

Abstract: An exemplary semiconductor device includes a clock generator circuit configured to generate a clock signal, and a duty cycle adjustment circuit configured to receive the clock signal. The duty cycle adjustment circuit includes an adjuster circuit configured to receive a back-bias voltage and to adjust a duty cycle of the clock signal based on the back-bias voltage to provide an output clock signal.

公开(公告)号：US10580478B2

公开(公告)日：2020-03-03

申请号：US16593675

申请日：2019-10-04

Applicant: Micron Technology, Inc.

Inventor： Michael V. Ho

IPC: G11C11/16 ,  G11C11/4076 ,  G11C7/22 ,  G11C11/4093 ,  G06F13/16 ,  G11C7/10

Abstract: A semiconductor device may include a number of memory banks, an output buffer that couples to the memory banks, a number of switches that couple a voltage source to the output buffer, and a stagger delay circuit. The stagger delay circuit may include a resistor-capacitor (RC) circuit that outputs a current signal that corresponds to a data voltage signal received by the RC circuit. The stagger delay circuit may also include a logic circuit that determines a strength of the current signal and sends a first gate signal to a first portion of the switches based on the strength.

公开(公告)号：US10460791B2

公开(公告)日：2019-10-29

申请号：US15924757

申请日：2018-03-19

Applicant: Micron Technology, Inc.

Inventor： Michael V. Ho

IPC: G11C11/16 ,  G11C11/4076 ,  G11C7/22 ,  G06F13/16

Abstract: A semiconductor device may include a number of memory banks, an output buffer that couples to the memory banks, a number of switches that couple a voltage source to the output buffer, and a stagger delay circuit. The stagger delay circuit may include a resistor-capacitor (RC) circuit that outputs a current signal that corresponds to a data voltage signal received by the RC circuit. The stagger delay circuit may also include a logic circuit that determines a strength of the current signal and sends a first gate signal to a first portion of the switches based on the strength.

公开(公告)号：US10403353B1

公开(公告)日：2019-09-03

申请号：US15976705

申请日：2018-05-10

Applicant: Micron Technology, Inc.

Inventor： Michael V. Ho ,  Ravi Kiran Kandikonda

IPC: G11C11/40 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4093

Abstract: Devices, systems, and methods for reducing noise couplings between propagation lines for size efficiency. In one embodiment, a memory device is provided, comprising a memory array and an input/output (I/O) circuit. The I/O circuit can include a first plurality of global data lines and a second plurality of global data lines. The second plurality of global data lines are directly interleaved between the first plurality of global date lines and are configured to shield the first plurality of global data lines. In some embodiments, the first plurality of global data lines are shorter in length than the second plurality of global data lines and are switched before the second plurality of global data lines are switched.

公开(公告)号：US11217298B2

公开(公告)日：2022-01-04

申请号：US16817095

申请日：2020-03-12

Applicant: Micron Technology, Inc.

Inventor： Younghoon Oh ,  Michael V. Ho

IPC: G11C11/4076 ,  G11C11/4096 ,  H03L7/081 ,  G11C7/10 ,  G11C11/4093

Abstract: An apparatus includes a memory device interface comprising a first data output, a second data output, a third data output, and a fourth data output, as well as a first path corresponding to the first data output, a second path corresponding to the second data output, a third path corresponding to the third data output, and a fourth path corresponding to the fourth data output. The apparatus also includes a signal transmission circuit comprising a first output that when in operation transmits a first clock signal to the first path, the second path, the third path, and the fourth path and a second output that when in operation transmits a second clock signal to the first path, the second path, the third path, and the fourth path.